Integrated circuit structures having front-side-guided backside source or drain contacts are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, and has a backside contact structure thereon. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, and has a backside dielectric structure thereon, the backside dielectric structure laterally spaced apart from the backside contact structure. A dielectric gate cut plug is in contact with an end of the backside dielectric structure and with an end of the backside contact structure.

One aspect of the present disclosure pertains to a semiconductor structure. The semiconductor structure includes a first circuit area having: an active region extending lengthwise along a first direction, the active region includes a channel region between source/drain (S/D) features and a gate over the channel region, a dielectric structure over and surrounding the active region, a metal contact penetrating through a top surface of the dielectric structure to land on one of the S/D features, and a first via landing on the metal contact. The semiconductor structure includes a second circuit area having: the dielectric structure, a feedthrough via penetrating through the top surface of the dielectric structure and a bottom surface of the dielectric structure, and a second via landing on the feedthrough via. The first via and the second via have substantially coplanar bottom surfaces.

A semiconductor device includes a substrate including a fin-type active area and a device separation layer configured to cover both sidewalls of the fin-type active area, a pair of nanosheet stacks each including a lower nanosheet stack arranged on the fin-type active area and an upper nanosheet stack arranged on the lower nanosheet stack, an intermediate insulating layer arranged between the lower nanosheet stack and the upper nanosheet stack, a nanosheet separation wall arranged between each of the pair of nanosheet stacks and extending in a first horizontal direction, and a pair of gate lines extending on the pair of nanosheet stacks in a second horizontal direction, wherein the nanosheet separation wall separates respective lower nanosheet stacks in the pair of nanosheet stacks from each other in the second horizontal direction.

Provided is a semiconductor device which includes: a 1.sup.st transistor including a 1.sup.st channel structure extended in a 1.sup.st direction, and a 1.sup.st gate structure on the 1.sup.st channel structure; a 2nd transistor comprising a 2.sup.nd channel structure extended in the 1.sup.st direction, and a 2.sup.nd gate structure on the 2.sup.nd channel structure, the 2.sup.nd transistor being disposed adjacent to the 1.sup.st transistor in a 2.sup.nd direction that horizontally intersects the 1.sup.st direction; a 1.sup.st isolation wall between the 1.sup.st channel structure and the 2.sup.nd channel structure; and a 1.sup.st gate cut structure between the 1.sup.st gate structure and the 2.sup.nd gate structure on the 1.sup.st isolation wall in a 3.sup.rd direction that vertically intersects the 1.sup.st direction and the 2.sup.nd direction.

A semiconductor device includes a substrate with a planar top surface. At least a first gate cut stressor within a first gate cut region separates a first transistor region from a second transistor region. The first gate cut stressor is directly upon the planar top surface and applies a first tensile force perpendicular to a channel of the first transistor region and perpendicular to a channel of the second transistor region. The tensile force may improve hole and/or electron mobility within a transistor in the first transistor region and within a transistor in the second transistor region. The gate cut stressor may include a lower material within the gate cut region and an upper material upon the lower material. Alternatively, the gate cut stressor may include a liner material that lines the gate cut region and an inner material upon the liner material.

A semiconductor device may include a substrate, a lower power line in a lower portion of the substrate, metal layers on the substrate, and a protection structure that is electrically connected to the lower power line and the metal layers. The protection structure may include a doping pattern in the substrate, and a first source/drain pattern that is on the substrate and is electrically connected to an upper portion of the doping pattern. The doping pattern and the first source/drain pattern may include different dopants from each other.

A chip includes one or more first channels extending in a first direction, a first epitaxial (epi) layer coupled to the one or more first channels, one or more second channels extending in the first direction, a second epi layer coupled to the one or more second channels, and a dielectric wall disposed between the first epi layer and the second epi layer.

A semiconductor structure includes a substrate, two source/drain (S/D) features; channel layers connecting the S/D features; and a gate structure wrapping around each of the channel layers. The gate structure includes a gate electrode over a gate dielectric layer. The semiconductor structure further includes outer spacers disposed on two opposing sidewalls of the gate structure, inner spacers disposed laterally between the gate structure and each of the two S/D features, a gate-end dielectric feature directly contacting an end of the gate structure, and a gate-top dielectric layer. The gate-end dielectric feature directly contacts the gate electrode. A material in the gate-end dielectric feature has a higher dielectric constant than materials in the outer spacers and the inner spacers. Top surfaces of the gate-top dielectric layer and the gate-end dielectric feature are substantially coplanar. The gate-top dielectric layer is disposed directly above both the gate structure and the outer spacers.

Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.

A semiconductor structure according to the present disclosure includes a substrate, a first base fin and a second base fin arising from the substrate, an isolation structure disposed between the first base fin and the second base fin, first channel members disposed over the first base fin, second channel members disposed over the second base fin, a region isolation feature extending into the substrate, a first gate structure wrapping around each of the first channel members, second gate structure wrapping around each of the second channel members, a first gate cut feature extending through the first gate structure and into the isolation feature, and a second gate cut feature extending though the second gate structure and into the isolation feature. Each of the first gate cut feature and the second gate cut feature are spaced apart from the region isolation feature.