A semiconductor device includes a substrate, a plurality of transistor structures disposed on the substrate and spaced apart from each other in a first direction parallel to a surface of the substrate, each of the plurality of transistor structures including a lower portion active pattern and an upper portion active pattern spaced apart from the lower portion active pattern in a second direction intersecting the first direction, a gate cut film disposed between two adjacent transistor structures of the plurality of transistor structures, for each lower portion active pattern, a first layer that surrounds a portion of the lower portion active pattern, and a second layer disposed on each first layer. Each of the plurality of transistor structures includes a first work-function film surrounding the first portion of the lower portion active pattern and a second work-function film that surrounds a portion of the upper portion active pattern.

A semiconductor device and the method of forming the same are provided. The semiconductor device may include a first source/drain region, a first nanostructure on a first sidewall of the first source/drain region, a first gate structure around the first nanostructure, a first inner spacer on the first sidewall of the first source/drain region, a second inner spacer on a second sidewall of the first source/drain region, a first dielectric liner on a sidewall of the second inner spacer, and a first isolation feature on a sidewall of the first dielectric liner. The first inner spacer may be between the first gate structure and the first source/drain region. The second inner spacer may be between the first dielectric liner and the first source/drain region. The first dielectric liner may be between the first isolation feature and the second inner spacer.

A semiconductor device includes a substrate, first, second, and third fins protruding from the substrate, first, second and third source/drain (S/D) features over the first, second, and third fins, respectively, a first isolation feature over the substrate and disposed between the first and second S/D features, a second isolation feature over the substrate and disposed between the second and third S/D features, and a dielectric layer disposed on sidewalls of the first, second, and third S/D features and on sidewalls of the first and second isolation features. A top surface of the first isolation feature is above a top surface of the second isolation feature.