Techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

A semiconductor structure includes nanostructures vertically stacked above a substrate, a gate structure wrapping around at least one of the nanostructures, a gate spacer extending along a sidewall of the gate structure, a source/drain feature abutting the nanostructures, and inner spacers interposing the source/drain feature and the gate structure. The source/drain feature includes a first epitaxial layer and a second epitaxial layer. A dopant concentration in the first epitaxial layer is less than a dopant concentration of the second epitaxial layer. The first epitaxial layer separates the second epitaxial layer from the nanostructures. The first epitaxial layer has a straight sidewall extending continuously from a sidewall of a topmost one of the nanostructures to a sidewall of a bottommost one of the nanostructures.

Provided are multi-gate devices and methods for fabricating such devices. A method includes forming a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure have different structural configurations; performing a single etching process on the first gate structure and second gate structure to simultaneously form openings of different depths; and forming isolation material in the openings.

A semiconductor device may include: a field insulating layer; a first gate electrode disposed on the field insulating layer; a plurality of first nanosheets disposed in the first gate electrode; a second gate electrode disposed on the field insulating layer and forming a boundary with the first gate electrode; a plurality of second nanosheets disposed in the second gate electrode; and a gate pattern bridge disposed between the first gate electrode and the second gate electrode and contacting the boundary.

A semiconductor device includes a lower interlayer insulating layer including a first surface and a second surface that are opposite to each other in a first direction; a plurality of active patterns disposed on the first surface of the lower interlayer insulating layer; a gate structure disposed on the first surface of the lower interlayer insulating layer; a source/drain pattern connected to the plurality of active patterns; a lower conductive layer that is disposed on the second surface of the lower interlayer insulating layer and includes a first surface and a second surface; a lower source/drain contact protruding from the lower conductive layer in the first direction and connected to the source/drain pattern; and a contact separation pattern that penetrates the lower conductive layer and is in contact with the lower interlayer insulating layer.

Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first pair of field effect transistors (FETs). Additionally, the semiconductor structure includes a second pair of FETs. Further, the semiconductor structure includes a shallow gate cut that separates a first pair of gates, a first pair of channels, and a first pair of source/drain (S/D) epitaxies of the first pair of FETs. Additionally, the first pair of S/D epitaxies are wired to a backside power rail (BPR) by a backside contact. Further, the semiconductor structure includes a deep gate cut that separates a second pair of S/D epitaxies of the second pair of FETs. Additionally, one of the second pair of S/D epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact. Further, another of the second pair of S/D epitaxies is wired to the BPR by a backside contact.

An exemplary flowable chemical vapor deposition method includes depositing a flowable dielectric material over a substrate, ultraviolet curing the flowable dielectric material, and annealing the ultraviolet cured, flowable dielectric material. The flowable dielectric material fills a space between a first gate structure and a second gate structure. An ultraviolet power of the ultraviolet curing is greater than about 80%, and an annealing temperature of the annealing is less than about 500 C. A thickness of the flowable dielectric material deposited over tops of the first gate structure and the second gate structure is less than about 200 nm. The ultraviolet power, the temperature, and an as-deposited thickness may be selected based on germanium pile up characteristics expected at an inner spacer/source/drain interface.

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate between two adjacent semiconductor layers, a supporting layer disposed between the S/D feature and the substrate, the supporting layer having a curved top surface, a dielectric spacer disposed between and in contact with one of the semiconductor layers and the substrate, wherein the dielectric spacer, the substrate, the supporting layer, and a bottom surface of the S/D feature define an air gap therein.

A semiconductor device structure is provided. The semiconductor device structure includes a source/drain (S/D) feature disposed over a substrate and between two adjacent semiconductor layers, an inner spacer disposed between and in contact with one of the semiconductor layers and the substrate, and a dielectric layer structure disposed between the S/D feature and the substrate, the dielectric layer structure comprising a first dielectric layer in contact with the inner spacer and the substrate, and a second dielectric layer nested within the first dielectric layer, wherein a bottom surface and sidewall surfaces of the second dielectric layer are in contact with the first dielectric layer, and a bottom surface of the S/D feature, the first dielectric layer, the second dielectric layer, and the inner spacer define an air gap therebetween.

An exemplary gate stack includes a gate dielectric (e.g., a high-k dielectric layer over an interfacial layer) and a gate electrode (e.g., a work function layer over the high-k dielectric layer, a cap over the work function layer, and a bulk fill layer over the cap). The gate stack wraps and/or surrounds a first semiconductor layer disposed over a second semiconductor layer. The gate dielectric and the work function layer (and not the cap and/or the bulk fill layer) fill a space between the first semiconductor layer and the second semiconductor layer. A ratio of oxygen in outer portions of the gate stack to inner portions of the gate stack may be about 1 to about 1.25. A thickness of the work function layer at inner portions of the gate stack may be less than a thickness of the work function layer at outer portions of the gate stack.