An exemplary method for forming a gate stack of a multigate device includes forming a gate dielectric over a channel layer and forming a gate electrode over the gate dielectric. Forming the gate electrode includes forming a work function layer over the gate dielectric and forming a cap over the work function layer. Forming the cap includes forming a metal nitride layer over the work function layer and forming a silicon-comprising layer over the metal nitride layer. Forming the gate electrode includes forming a fluorine-free tungsten layer over the silicon-comprising layer of the cap without breaking vacuum. Forming the fluorine-free tungsten layer over the silicon-comprising layer includes co-flowing a tungsten-comprising precursor (e.g., WCl.sub.5) and a hydrogen-comprising precursor (e.g., H.sub.2).

A semiconductor structure according to the present disclosure includes a substrate, a first source/drain feature and a second source/drain feature disposed over the substrate, and a plurality of nanostructures extending between the first source/drain feature and the second source/drain feature. Each of the first source/drain feature and the second source/drain feature includes a first epitaxial layer in contact with sidewalls of the plurality of nanostructures and a second epitaxial layer spaced apart from the sidewalls of the plurality of nanostructures by the first epitaxial layer. The first epitaxial layer includes a semiconductor material doped with carbon (C) and boron (B).

In one embodiment, a complementary field effect transistor (CFET) device includes one or more metallization layers between stacked transistors.

Gate layouts and/or devices implementing gate support structures (e.g., gate bars) to in non-active region areas (e.g., isolation regions), along with methods of fabrication thereof, are described herein. An exemplary gate support structure is connected to at least two gates (e.g., two to six, in some embodiments) that are disposed in a non-active region area. The at least two gates extend lengthwise along a first direction, and the gate support structure extends lengthwise along a second direction that is different than the first direction. The gate support structure and the at least two gates may be disposed on a substrate isolation structure, such as a shallow trench isolation (STI) structure. A composition and/or configuration of the gate support structure may be the same as or different than a composition and/or a configuration of the at least two gates.

The present disclosure provides an integrated circuit (IC) structure in accordance with some embodiments. The IC structure includes a circuit structure having semiconductor devices formed on a first substrate, an interconnect structure over the semiconductor devices; and a thermal dissipation structure formed on a second substrate. The second substrate is boned to the circuit structure such that the thermal dissipation structure is interposed between the first and second substrates. The thermal dissipation structure includes a diamond-like carbon (DLC) layer. The DLC layer includes a bottom portion having large grain sizes and a top portion having fine DLC grain sizes.

A semiconductor device and a method of forming the same are provided. The method includes forming a semiconductor fin extending from a substrate. A dummy gate stack is formed over the semiconductor fin. The dummy gate stack extends along sidewalls and a top surface of the semiconductor fin. The semiconductor fin is patterned to form a recess in the semiconductor fin. A semiconductor material is deposited in the recess. An implantation process is performed on the semiconductor material. The implantation process includes implanting first implants into the semiconductor material and implanting second implants into the semiconductor material. The first implants have a first implantation energy. The second implants have a second implantation energy different from the first implantation energy.

A 3D semiconductor device, the device including: a first level including single crystal first transistors, a first metal layer, and a first isolation layer; a second level including second transistors and a second isolation layer, where the first level is overlaid by the second level; a third level including single crystal third transistors, where the second level is overlaid by the third level, where the third level includes a third isolation layer, where the third level is bonded to the second level; and a power delivery path to the second transistors, where at least a portion of the power delivery path is connected to at least one of the first transistors.

Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.

Methods and devices that include forming a first epitaxial region and a second epitaxial region above the first epitaxial region. An opening may be formed extending from the first region to the second region. And a liner layer is deposited on a sidewall and a bottom of the opening. A plasma treatment is performed on the liner layer, which can form a conditioned or passivated region of the first epitaxial region that may be maintained during the growth of additional epitaxial material on the second epitaxial region.

Semiconductor devices and methods of manufacture are presented. In embodiments a method of manufacturing the semiconductor device includes forming a fin from a plurality of semiconductor materials, depositing a dummy gate over the fin, depositing a plurality of spacers adjacent to the dummy gate, removing the dummy gate to form an opening adjacent to the plurality of spacers, widening the opening adjacent to a top surface of the plurality of spacers, after the widening, removing one of the plurality of semiconductor materials to form nanowires, and depositing a gate electrode around the nanowires.