A method of fabricating a semiconductor device includes providing a partially-fabricated semiconductor device including a dummy gate structure disposed over a semiconductor layer stack. In some embodiments, the method further includes removing the dummy gate structure and at least a portion of each semiconductor layer of the semiconductor layer stack to form a trench. In some examples, the method further includes forming one or more refill layers in a bottom portion of the trench and forming one or more refill layers in a top portion of the trench over the bottom portion of the trench. In some embodiments, the one or more refill layers in the top and bottom portions of the trench respectively define top and bottom portions of an isolation structure. In some examples, at least one refill layer of respective ones of the top and bottom portions of the isolation structure have a different material composition.

A method of forming a semiconductor device, the method including forming a superlattice structure on a substrate, the superlattice structure including a plurality of first layers and a corresponding plurality of second layers, the first layers and the second layers being alternatingly arranged in a plurality of stacked pairs; forming one or more gate and gate spacers in a gate region on the substrate; forming a plurality of nanosheets from the superlattice structure; filling the corresponding plurality of voids with a plurality of dummy dielectric interlayers; etching the plurality of nanosheets between the one or more gate and gate spacers to form one or more source regions and one or more drain regions; forming an inner spacer on the plurality of dummy dielectric interlayers; and depositing a source material in the one or more source regions and a drain material in the one or more drain regions.

A method includes forming a stack of nanostructures over a substrate; forming a recess in the substrate adjacent the stack of nanostructures, wherein the recess exposes sidewalls of the stack of nanostructures; depositing a continuous semiconductor seed layer in the recess and extending along the sidewalls of the stack of nanostructures; epitaxially growing a source/drain region on the semiconductor seed layer; after epitaxially growing the source/drain region, forming inner spacers between adjacent nanostructures of the stack of nanostructures; and forming a gate structure between adjacent nanostructures of the stack of nanostructures.

Provided is a semiconductor device which includes: a substrate; a channel structure on the substrate; a source/drain pattern connected to the channel structure; a gate structure on the channel structure; an inner spacer structure comprising an inner spacer between the source/drain pattern and the gate structure, and an inner spacer residue connected to the inner spacer structure; and an inner isolation structure between the inner spacer residue and a bottom surface of the source/drain pattern.

A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed, a contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.

Provided is a semiconductor device which includes: a 1.sup.st source/drain pattern for a 1.sup.st transistor; a 2.sup.nd source/drain pattern for a 2.sup.nd transistor, above the 1.sup.st source/drain pattern, the 2.sup.nd source/drain pattern having a smaller width than the 1.sup.st source/drain pattern in a channel-width direction; a 1.sup.st isolation layer surrounding the 1.sup.st source/drain pattern; a 2.sup.nd isolation layer surrounding the 2.sup.nd source/drain pattern, the 1.sup.st and 2.sup.nd isolation layers including a first material; a liner surrounding the 1.sup.st source/drain pattern, the liner including a 2.sup.nd material; and a contact structure on the 1.sup.st source/drain pattern, wherein the contact structure penetrates the 2.sup.nd isolation layer and the liner to contact the 1.sup.st source/drain pattern without penetrating the 1.sup.st isolation layer.

Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The method includes forming a fin structure from a substrate, and the fin structure includes a plurality of semiconductor layers. The method further includes depositing a gate dielectric layer around a portion of each semiconductor layer of the plurality of semiconductor layers, depositing an adhesion layer on the gate dielectric layer, and the adhesion layer surrounds the portion of each semiconductor layer of the plurality of semiconductor layers. The method further includes depositing a fluorine-containing layer on the adhesion layer, and the fluorine-containing layer surrounds the portion of each semiconductor layer of the plurality of semiconductor layers. The method further includes performing an annealing process on the fluorine-containing layer, removing the fluorine-containing layer and the adhesion layer, and forming a gate electrode layer on the gate dielectric layer.

Method to form low-contact-resistance contacts to source/drain features are provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, selectively depositing a first silicide layer on the surface of the p-type source/drain feature while the surface of the n-type source/drain feature is substantially free of the first silicide layer, depositing a metal layer on the first silicide layer and the surface of the n-type source/drain feature, and depositing a second silicide layer over the metal layer. The selectively depositing includes passivating the surface of the surface of the n-type source/drain features with a self-assembly layer, selectively depositing the first silicide layer on the surface of the p-type source/drain feature, and removing the self-assembly layer.

A 3D semiconductor device, the device including: a first level including a first single crystal layer and including first transistors each of which includes a single crystal channel; a first metal layer; a second metal layer overlaying the first metal layer; a second level including second transistors and overlaying the second metal layer, each of first memory cells include at least one second transistor; a third level including third transistors and overlaying the second level; a fourth level including fourth transistors and overlaying the third level, each of second memory cells include at least one fourth transistor, where at least one of the second transistors includes a metal gate, where the first level includes memory control circuits which control writing to the second memory cells, and at least one of the second transistors includes a hafnium oxide gate dielectric.

Provided is a semiconductor device which includes: a substrate; a channel structure on the substrate; a source/drain pattern connected to the channel structure; a gate structure on the channel structure; an inner spacer structure comprising an inner spacer between the source/drain pattern and the gate structure, and an inner spacer residue connected to the inner spacer structure; and an inner isolation structure between the inner spacer residue and a bottom surface of the source/drain pattern.