A stack includes a first power semiconductor device in a first chip and a second power semiconductor device in a second chip. The first power semiconductor device is configured for active operation during which an application load current is conducted by the first power semiconductor device and power losses occur in the first power semiconductor device. The second power semiconductor device is configured for passive operation during which a voltage is blocked. The stack further includes a heat sink interface configured to dissipate the power losses. The second chip is arranged between the first chip and the heat sink interface.

An electronic module, including: a first conductive plate which contains copper or a first copper alloy as a main component thereof; a second conductive plate which has a main surface that faces the first conductive plate and has a side surface that extends continuously from the main surface, and which contains copper or a second copper alloy as a main component thereof; and a first metal oxide layer which is provided on the main surface and the side surface of the second conductive plate, and which contains a first metal oxide that is of a metal different from a metal of the second conductive plate and is electrically insulating.

A memory device can include an array of memory cells and an integrated inductor. The array can be provided on a first semiconductor substrate. First conductive portions of the inductor can be provided on the first semiconductor substrate, and each of the first conductive portions provides less than one revolution of a conductive path of the inductor. Second conductive portions of the inductor can be vertically separate from the first conductive portions and coupled to the first conductive portions to provide multiple revolutions of the conductive path of the inductor. The second conductive portions of the inductor can be provided on a different second semiconductor substrate. The inductor can optionally include a core region that is filled with a magnetic or non-magnetic material.

A semiconductor structure and a method of fabricating the structure are disclosed. The semiconductor structure includes a substrate, a device layer disposed on the substrate, a power line disposed on the device layer, a first capacitor circuit, a second capacitor circuit, and a control circuit disposed on the power line and configured to control the first capacitor circuit. The first capacitor circuit includes a first conductive via disposed on the power line, a first conductive line disposed on the first conductive via and aligned to a first side of the power line, and a first trench capacitor disposed on the first conductive line. The second capacitor circuit includes a second conductive via disposed on the power line, a second conductive line disposed on the second conductive via and aligned to a second side of the power line, and a second trench capacitor disposed on the second conductive line.

A half-bridge module has a carrier including a conductor track layer. The conductor track layer has a first transistor strip section, a second transistor strip section and an intermediate section, each extending along a first direction. The intermediate section is arranged between the first transistor strip section and the second transistor strip section. Connecting surface sections of a first surface, which also extends in the first transistor strip section, extend in the intermediate section. Connection surfaces insulated therefrom alternate with the connecting surface sections in the first direction.

A half-bridge module has a carrier including a conductor track layer. The conductor track layer has a first transistor strip section, a second transistor strip section and an intermediate section, each extending along a first direction. The intermediate section is arranged between the first transistor strip section and the second transistor strip section. Connecting surface sections of a first surface, which also extends in the first transistor strip section, extend in the intermediate section. Connection surfaces insulated therefrom alternate with the connecting surface sections in the first direction.

A High Electron Mobility Transistor, (HEMT), structure having a gate, a source and a drain, the HEMT structure including a depletion-mode transistor having a breakdown voltage, current limiting means arranged for ensuring that a drain source current of the HEMT structure, in an off-state of the HEMT structure, is at most 20 nA/mm, being a current per unit gate length of the depletion-mode transistor, the HEMT structure can include just the depletion-mode transistor or a cascode configuration of a depletion-mode transistor with an enhancement mode transistor.

Provided is a semiconductor device including an upper arm circuit and a lower arm circuit and having a positive electrode terminal, a negative electrode terminal, and an output terminal, which includes an insulating plate; a first wiring pattern provided on the insulating plate; and a second wiring pattern provided on the insulating plate and spaced apart from the first wiring pattern, the upper arm circuit has a circuit in which the positive electrode terminal, a first diode portion provided on the first wiring pattern, a first transistor portion connected in series with the first diode portion and provided on the first wiring pattern, and the output terminal are connected and arranged in this order, and the lower arm circuit has a second transistor portion provided on the second wiring pattern, and a second diode portion provided on the second wiring pattern.

Provided is a semiconductor device including an upper arm circuit and a lower arm circuit and having a positive electrode terminal, a negative electrode terminal, and an output terminal, which includes an insulating plate; a first wiring pattern provided on the insulating plate; and a second wiring pattern provided on the insulating plate and spaced apart from the first wiring pattern, the upper arm circuit has a circuit in which the positive electrode terminal, a first diode portion provided on the first wiring pattern, a first transistor portion connected in series with the first diode portion and provided on the first wiring pattern, and the output terminal are connected and arranged in this order, and the lower arm circuit has a second transistor portion provided on the second wiring pattern, and a second diode portion provided on the second wiring pattern.

A semiconductor device includes: a first transformer; a second transformer; a first rectifier chip; a second rectifier chip; and a first frame. Each of the first rectifier chip and the second rectifier chip includes: a first output pad and a second output pad; a semiconductor substrate of a first conductivity type including a first surface; a first semiconductor region of a second conductivity type disposed on the first surface; a first transistor provided in the first semiconductor region and electrically connected to the first output pad; and a second semiconductor region of the second conductivity type provided at a position spaced apart from the first transistor in the first semiconductor region and electrically connected to the second output pad. The second semiconductor region is in contact with the semiconductor substrate. The first rectifier chip and the second rectifier chip are disposed to be spaced apart from each other.