A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.

A reactive power-voltage control method for integrated transmission and distribution networks is provided. The reactive power-voltage control method includes: establishing a reactive power-voltage control model for a power system consisting of a transmission network and a plurality of distribution networks; performing a second order cone relaxation on a non-convex constraint of the plurality of distribution network constraints to obtain the convex-relaxed reactive power-voltage control model; solving the convex-relaxed reactive power-voltage control model to acquire control variables of the transmission network and control variables of each distribution network; and controlling the transmission network based on the control variables of the transmission network and controlling each distribution network based on the control variables of the distribution network, so as to realize coordinated control of the power system.

A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

Energy consumption modelling requires to consider various factors affecting the energy consumption in buildings, to be able to effectively forecast future consumption. Even though some of the state of the art deep learning based approaches are able to address these requirements to some extent, they are computationally heavy. The disclosure herein generally relates to energy forecasting, and, more particularly, to a method and system for graph signal processing (GSP) based energy modelling and forecasting. The system monitors and collects information on energy consumption in a building and values of associated energy consumption parameters. This input data is further processed using GSP to generate a building energy consumption model, from which a smooth signal is obtained by applying total variation minimization. The system further performs forecasting using the smooth signal.

Various examples are provided related to automated chip design, such as a pareto-optimization framework for automated network-on-chip design. In one example, a method for network-on-chip (NoC) design includes determining network performance for a defined NoC configuration comprising a plurality of n routers interconnected through a plurality of intermediate links; comparing the network performance of the defined NoC configuration to at least one performance objective; and determining, in response to the comparison, a revised NoC configuration based upon iterative optimization of the at least one performance objective through adjustment of link allocation between the plurality of n routers. In another example, a method comprises determining a revised NoC configuration based upon iterative optimization of at least one performance objective through adjustment of a first number of routers to obtain a second number of routers and through adjustment of link allocation between the second number of routers.

A method for forming an integrated circuit (IC) is provided. The method includes the following operations. A circuit layout including a first load region and a second load region is received. A full power network of the circuit layout is obtained. The full power network is transformed into a first power network according to the first load region. A first power simulation is performed upon the first power network. The full power network is transformed into a second power network according to the second load region. A second power simulation is performed upon the second power network. The IC is fabricated according to the circuit layout.

A gear-based mechanical metamaterial with continuously adjustable elastic parameters in a large range is provided. The gear-based mechanical metamaterial includes a gear array, a frame and connecting shafts. The gear array is formed by periodically extending mechanical metamaterial cells along an x direction and a y direction. Each of the mechanical metamaterial cells is formed by arranging a multiple gears. Adjacent gears of the multiple gears are meshed with each other. Each of the multiple gears includes a center hole and two centrosymmetric irregularly-shaped holes. A thickness of an elastic arm between the each of two centrosymmetric irregularly-shaped holes and an outer wall of a corresponding one of the multiple gears is uniformly increased or decreased. Each of the connecting shafts is arranged in a center hole of a corresponding one of the multiple gears.

Electromagnetic transient simulation method applicable to a field programmable gate array (FPGA), which integrates topological parameters of a circuit to be simulated into two matrix parameters in an initialization stage thereof; and voltage and current information at each simulation moment can be obtained only through simple matrix multiplication operation in a main part of the simulation cycle thereof. The method avoids complex initialization operation in the field programmable logic array; meanwhile, the flow of the main part of the simulation cycle in the FPGA is maximally compressed, and the efficiency of electromagnetic transient simulation based on the FPGA is greatly improved.

A data storage device including, in one implementation, a number of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density that includes one or more memory dies. The die density of each memory die package is configured to provide an even thermal distribution across the number of memory die packages. The respective die densities of two memory of the die packages are different from each other.

A dynamic power consumption estimation method includes recording a statistical value of each of n target signals of a to-be-measured target in a unit time, where the target signal is a clock signal obtained after clock gating and the statistical value is a quantity of times toggling, or the target signal is a clock gating signal and the statistical value is a quantity of enable cycles, and calculating the dynamic power consumption of the to-be-measured target in the unit time based on the statistical value of each of the n target signals in the unit time.