In some embodiments, a method of generating a cell in a layout diagram includes: selecting a cell from a library of standard cells, components of the cell defining an active circuit; identifying a dummy device within the cell that is disconnected from the active circuit within the cell; and connecting the dummy device to a target node of the active circuit.

An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.

Aspects relate to monitoring timing margin of logic paths and its degradation through an integrated circuit. In one example an integrated circuit has a logic path formed in the integrated circuit. A monitor circuit is formed in the integrated circuit near the logic path and configured to monitor a condition of the logic path and to generate a diagnostic code sequence to indicate the condition of the logic path over time. A monitor controller is configured to receive diagnostic codes of the diagnostic code sequence, to determine a condition of the integrated circuit based on the diagnostic code sequence, and to initiate a remedial action in response to the condition of the integrated circuit.

Various embodiments provide for modifying a circuit design based on timing tradeoff, which can be part of an electronic design automation (EDA) system. For instance, some embodiments use a return on investment (ROI) concept to determine one or more thresholds for how much area or power of a circuit design should be available for use (e.g., sacrificed) in order to obtain an improvement in slack by a given transformation.

Some embodiments provide a method calculating parasitic parameters for an IC design layout having interconnects that traverse multiple interconnect layers. The interconnects represent wires that traverse multiple wiring layers of the IC. The method analyzes congestion of interconnects in a layer of the design layout to identify at least a first region of the layer having a first density of interconnects and a second region of the layer having a second, greater density of interconnects. The method divides the design layout into multiple tiles such that each interconnect of a set of the interconnects is divided into multiple interconnect segments each of which is located in a respective tile. Tiles in the first region are larger than tiles in the second region to account for the different interconnect densities. The method computes parasitic values that express parasitic effects exerted on the interconnect segments on a per-tile basis.

Some embodiments provide a method for calculating parasitics for an IC design layout that on at least one layer includes neighboring interconnects that are neither parallel nor perpendicular to each other. The method divides the layout into tiles such that each of a set of interconnects is divided into segments each of which is located in a respective tile. Each tile of a set of the tiles includes two or more segments that are neither parallel nor perpendicular. For each segment located in a tile, the method uses a parasitic value solver to compute a set of parasitic values representing parasitic effects exerted on the segment by a set of other segments in the tile and a set of neighboring tiles. For each interconnect, the method computes a set of overall parasitic values based on the parasitic values computed for the segments of the interconnect.

Some embodiments provide a method for calculating parasitic parameters for an IC design layout including interconnects that traverse one or more interconnect layers and represent wires traversing one or more wiring layers of the IC. The method divides the design layout into tiles such that each interconnect of a set of the interconnects is divided into interconnect segments each of which is located in a respective tile. For a first interconnect segment located in a first tile, the method uses (i) a first computation technique to compute a first parasitic value representing a parasitic effect between the first interconnect segment and a second interconnect segment located in the first tile and (ii) a second, different computation technique to compute a second parasitic value representing a parasitic effect between the first interconnect segment and a third interconnect segment located in a second tile that is a neighbor of the first tile.

Some embodiments provide a method for calculating parasitic capacitance for an IC design layout. The method iteratively selects a core region and a plurality of halo regions neighboring the core region. For each interconnect segment located in the core, the method computes a halo capacitance value representing parasitic capacitance exerted on the interconnect segment by a particular neighboring segment in a particular neighboring halo region that depends on the particular neighboring segment in the particular neighboring halo region in addition to at least one additional neighboring interconnect segment in another halo region. To account for first and second interconnect segments in neighboring regions having different computed halo capacitance values with respect to each other, the method computes a single capacitance value from the first and second computed halo capacitance values and uses the single capacitance value to represent the parasitic capacitance exerted between the first and second interconnect segments.

Some embodiments provide a method for calculating parasitic parameters for an IC design layout having interconnects that traverse multiple interconnect layers. The interconnects represent wires that traverse multiple wiring layers of the IC. The method divides the layout into 3D tiles such that each of a set of the interconnects is divided into multiple segments each of which is located in a 3D tile. Each 3D tile includes segments of a wiring layer. For a segment located in a particular 3D tile, the method computes parasitic values representing parasitic effects exerted on the segment by other segments in the particular 3D tile and a set of neighboring 3D tiles, including tiles with segments of the same wiring layer and tiles with segments of at least one other wiring layer. The method uses the set of parasitic values to determine parasitic effects exerted on an interconnect to which the segment belongs.

An acquisition unit (21) acquires a simulation period indicating an object period for which simulations of amounts of energy consumption in a building are to be done, a parallel number indicating the number of the simulations that are to be performed in parallel, and a holiday condition indicating nonoperating days of an air conditioning system installed in the building. A planning unit (22) splits the simulation period into the parallel number to generate split periods. The planning unit (22) splits the simulation period into the parallel number so that starting days of the split periods other than an initial split period may be the nonoperating days indicated by the holiday condition. A simulation unit (23) does the simulations of the amounts of energy consumption in the building in parallel, for the split periods.