A method includes patterning stacked layers to form a first multi-layer stack and a second multi-layer stack, each including a plurality of sacrificial layers and a plurality of nanostructures located alternatingly. The second multi-layer stack is wider than the first multi-layer stack. A nanosheet transistor is formed based on the first multi-layer stack. The nanosheet transistor includes first channel regions having a first width, and a first gate stack on the first channel regions. A nanowire transistor is formed based on the second multi-layer stack. The nanowire transistor includes second channel regions narrower than the first channel regions, and a second gate stack on the second channel regions.

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a substrate, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers is laterally etched, an insulating layer is formed on a sidewall of the source/drain space, the insulating layer is partially etched, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer, and a source/drain epitaxial layer is formed in the source/drain space. After the source/drain epitaxial layer is formed, an end face of at least one of the second semiconductor layers is covered by the remaining insulating layer.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure also includes a gate structure wrapping around the nanostructures and a first dielectric feature separating the gate structure into a first portion and a second portion. The semiconductor structure also includes a metal layer formed over the gate structure. In addition, top surfaces of the first portion and the second portion of the gate structure and a top surface of the first dielectric feature are covered by the metal layer.

The present disclosure describes a semiconductor device having an identification device for chip identification. The semiconductor structure includes first and second channel structures on a substrate, a gate structure on the first and second channel structures, an epitaxial structure on the first and second channel structures, and a first source/drain (S/D) contact structure on the first channel structure. The epitaxial structure is at a first side of the gate structure and the first S/D contact structure is at a second side of the gate structure opposite to the first side. The semiconductor structure further includes a second S/D contact structure on the second channel structure. The second S/D contact structure is at the second side of the gate structure.

Techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Integrated circuit (IC) static random-access memory (SRAM) bit-cell structures comprising pass-gate transistors having a different number of active channel regions than the number of active channel regions in pull-down transistors. A pass-gate transistor with fewer active channel regions than a pull-down transistor may reduce read instability of an SRAM bit-cell, and/or reduce overhead associated with read assist circuitry coupled to the bit-cell. In some examples, one or more pass-gate transistor channel regions are impurity doped or removed from either a top side or bottom side of the pass-gate transistors to depopulate the number of active channel regions relative to a pull-down transistor.

A strain-relaxed silicon/silicon germanium (Si/SiGe) bi-layer can be used as a foundation for constructing strained channel transistors in the form of nanosheet gate all-around field effect transistors (GAAFETs). The bi-layer can be formed using a modified silicon-on-insulator process. A superlattice can then be epitaxially grown on the bi-layer to provide either compressively strained SiGe channels for a p-type metal oxide semiconductor (PMOS) device, or tensile-strained silicon channels for an n-type metal oxide semiconductor (NMOS) device. Composition and strain of the bi-layer can influence performance of the strained channel devices.

An integrated circuit (IC) structure includes a fin structure protruding from a semiconductor substrate, the fin structure including a first portion having a first width, a second portion having a second width that is different from the first width, and a third portion extending continuously along a first direction over the semiconductor substrate, the first width and the second width being measured along a second direction perpendicular to the first direction. The IC structure also includes a first standard cell including a first metal gate stack engaged with the first portion, a second standard cell including a second metal gate stack engaged with the second portion, and a filler cell disposed between the first standard cell and the second standard cell, where the filler cell includes the third portion that connects the first portion to the second portion. The IC further includes a dielectric gate defining a first boundary of the filler cell and a third metal gate stack defining a second boundary of the filler cell, where the dielectric gate and the third metal gate stack are separated by a one-pitch spacing.

A method for forming a semiconductor structure is provided. The method includes forming a first active region in which first semiconductor layers and second semiconductor layers are alternatingly stacked over a first lower fin element. In a plan view, the active region includes a first portion and a second portion narrower than the first portion. The method also includes removing the first semiconductor layers of the first active region. The second semiconductor layers of the first portion of the first active region form first nanostructures, and the second semiconductor layers of the second portion of the first active region form second nanostructures. The method also includes forming a first gate stack to surround the first nanostructures, and forming a second gate stack to surround the second nanostructures.

A semiconductor apparatus may include a substrate including a first region and a second region; a first device on the first region; and a second device on the second region. The first device may include a channel structure including an insulating isolation pattern, first semiconductor patterns stacked under a lower surface of the insulating isolation pattern and including silicon germanium, and second semiconductor patterns stacked on an upper surface of the insulating isolation pattern and including silicon. The second device may include a semiconductor stack at a level corresponding to a level of the channel structure. The semiconductor stack may include an intermediate semiconductor layer, first lower semiconductor layers and second lower semiconductor layers alternately stacked under a lower surface of the intermediate semiconductor layer, and first upper semiconductor layers and second upper semiconductor layers alternately stacked on an upper surface of the intermediate semiconductor layer.