A method of forming a semiconductor device includes the following steps. A 2D material layer is formed over a bottom metal layer. A top metal layer is formed over the 2D material layer. An oxidation treatment is performed to the 2D material layer to form an oxide region interfacing both the 2D material layer and the top metal layer.

A device including one or more transistors with nano sheets stacked along a vertical direction, and a method of fabricating the device are disclosed herein. In some embodiments, a device includes a transistor structure including at least a first dielectric nano sheet and a second dielectric nano sheet. The first dielectric nano sheet and the second dielectric nano sheet may extend parallel to a substrate. The second dielectric nano sheet may be disposed above the first dielectric nano sheet. The transistor may include a first source/drain structure coupled to a first end of the first dielectric nano sheet and a first end of the second dielectric nano sheet, and a second source/drain structure coupled to a second end of the first dielectric nano sheet and a second end of the second dielectric nano sheet.

A device including one or more transistors with nano sheets stacked along a vertical direction, and a method of fabricating the device are disclosed herein. In some embodiments, a device includes a transistor structure including at least a first dielectric nano sheet and a second dielectric nano sheet. The first dielectric nano sheet and the second dielectric nano sheet may extend parallel to a substrate. The second dielectric nano sheet may be disposed above the first dielectric nano sheet. The transistor may include a first source/drain structure coupled to a first end of the first dielectric nano sheet and a first end of the second dielectric nano sheet, and a second source/drain structure coupled to a second end of the first dielectric nano sheet and a second end of the second dielectric nano sheet.

A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.

A semiconductor device includes a substrate, and a first transistor disposed on the substrate. The first transistor includes a first channel layer, a magnesium oxide layer, a first gate electrode, a first gate dielectric and first source/drain electrodes. A crystal orientation of the first channel layer is <100> or <110>. The magnesium oxide layer is located below the first channel layer and in contact with the first channel layer. The first gate electrode is located over the first channel layer. The first gate dielectric is located in between the first channel layer and the first gate electrode. The first source/drain electrodes are disposed on the first channel layer.

Semiconductor structures and methods of forming the same are provided. An exemplary semiconductor structure includes an isolation feature over a semiconductor substrate, a fin-shaped base protruding from the semiconductor substrate and through the isolation feature, first nanostructures vertically stacked above a top surface of the fin-shaped base, a middle dielectric layer disposed above the first nanostructures, a first barrier layer interfacing with a top surface of the middle dielectric layer, a second barrier layer interfacing with a bottom surface of the middle dielectric layer, second nanostructures vertically stacked above the middle dielectric layer, a bottom source/drain feature abutting at least one of the first nanostructures, a top source/drain feature abutting at least one of the second nanostructures, a bottom gate structure wrapping around at least one of the first nanostructures, and a top gate structure wrapping around at least one of the second nanostructures.

Semiconductor structures and methods of forming the same are provided. An exemplary semiconductor structure includes an isolation feature over a semiconductor substrate, a fin-shaped base protruding from the semiconductor substrate and through the isolation feature, first nanostructures vertically stacked above a top surface of the fin-shaped base, a middle dielectric layer disposed above the first nanostructures, a first barrier layer interfacing with a top surface of the middle dielectric layer, a second barrier layer interfacing with a bottom surface of the middle dielectric layer, second nanostructures vertically stacked above the middle dielectric layer, a bottom source/drain feature abutting at least one of the first nanostructures, a top source/drain feature abutting at least one of the second nanostructures, a bottom gate structure wrapping around at least one of the first nanostructures, and a top gate structure wrapping around at least one of the second nanostructures.

A method for manufacturing a semiconductor wafer includes steps of: preparing a peeling object including a single crystal body of a semiconductor having a pair of major surfaces composed of front and back surfaces, the peeling object having a peeling layer provided along at least one of the major surfaces; applying a tensile stress to the peeling object to cause a first major surface and a second major surface to be separated from each other; forming a stress-concentrated region in the peeling layer positioned inside an outer peripheral edge in a radial direction of which the center is a center axis orthogonal to the major surface; and propagating cracks from the stress-concentrated region as a starting point, thereby peeling between a first side portion and a second side portion of the peeling object having the peeling layer interposed therebetween in a direction parallel to the center axis.

A method for manufacturing a semiconductor wafer includes steps of: preparing a peeling object including a single crystal body of a semiconductor having a pair of major surfaces composed of front and back surfaces, the peeling object having a peeling layer provided along at least one of the major surfaces; applying a tensile stress to the peeling object to cause a first major surface and a second major surface to be separated from each other; forming a stress-concentrated region in the peeling layer positioned inside an outer peripheral edge in a radial direction of which the center is a center axis orthogonal to the major surface; and propagating cracks from the stress-concentrated region as a starting point, thereby peeling between a first side portion and a second side portion of the peeling object having the peeling layer interposed therebetween in a direction parallel to the center axis.

Devices, transistor structures, systems, and techniques are described herein related to field effect transistors having a stack of metal chalcogenide nanoribbons extending between a source and drain and contacted by a gate structure. The metal chalcogenide nanoribbons may be recrystallized using a local laser anneal treatment and/or a dopant may be applied, outside of a channel region of the metal chalcogenide nanoribbons, using a local laser treatment in the presence of a precursor including the dopant.