A superconducting fault current limiter element, comprising: a plurality of tapes, arranged in electrical parallel fashion among one another, wherein at least one tape of the plurality of tapes comprises a superconductor tape, and wherein at least one tape of the plurality of tapes comprises a non-superconductor tape.

A semiconductor-superconductor hybrid device comprises a semiconductor layer and a superconductor layer. The superconductor layer is arranged over an edge of the semiconductor layer so as to enable energy level hybridisation between the semiconductor layer and the superconductor layer. The semiconductor layer is arranged in a sandwich structure between first and second insulating layers, each insulating layer being in contact with a respective opposed face of the semiconductor layer. This configuration may allow for good control over the geometry of the semiconductor layer and may improve tolerance to manufacturing variations. The device may be useful in a quantum computer. Also provided is a method of manufacturing the device, and a method of inducing topological behaviour in the device.

A semiconductor-superconductor hybrid device comprises a semiconductor, a superconductor, and a barrier between the superconductor and the semiconductor. The device is configured to enable energy level hybridisation between the semiconductor and the superconductor. The barrier is configured to increase a topological gap of the device. The barrier allows for control over the degree of hybridisation between the semiconductor and the superconductor. Further aspects provide a quantum computer comprising the device, a method of manufacturing the device, and a method of inducing topological behaviour in the device.

An apparatus for controlling and monitoring the lifetime of a superconducting fault current limiter. The apparatus may include a processor; and a memory unit coupled to the processor, including a lifetime routine, where the lifetime routine is operative on the processor to monitor the superconducting fault current limiter. The lifetime routine may include a lifetime estimation processor to receive a set of fault information for a fault event of a superconductor tape of the superconducting fault current limiter, determine a present state of the superconductor tape based upon the set of fault information, and determine an estimated lifetime of the superconductor tape based upon the present state. The present state may be determined from additional information such as fault history on the superconducting fault current limiter, as well as a database of superconductor tape behavior with respect to various faults.

An electronic device (e.g., a superconducting memory cell) includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material is patterned to form a plurality of distinct instances of the layer of superconducting material including: a first wire; and a loop that is (i) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state. The loop is configured to form a persistent current via the capacitive coupling in response to a write current applied to the first wire while the loop and the first wire are in the superconducting state. The persistent current represents a logic state of the electronic device.

The various embodiments described herein include methods, devices, and systems for operating superconducting circuitry. In one aspect, a superconducting component includes: (1) a superconductor having a plurality of alternating narrow and wide portions, each wide portion having a corresponding terminal; and (2) a plurality of heat sources, each heat source thermally coupled to a corresponding narrow portion such that heat from the heat source is transmitted to the corresponding narrow portion; where the plurality of heat sources is electrically isolated from the superconductor.

A semiconductor device includes a transmission circuit coupled between a first voltage supply node and a second voltage supply node, and suitable for outputting an output data signal corresponding to a data value to an output terminal during a data output enable period, and a switching circuit coupled between the first and second voltage supply nodes, and suitable for providing a current path between the first and second voltage supply nodes during a data output disable period.

A method of protecting a high-voltage network comprising the steps for maintaining first controlled switches closed and second controlled switches open; measuring voltage and current on high-voltage interfaces; communicating the direction of the current to the other end of a high-voltage line; for each node: identifying a fault; verifying that the current is lower than the current interruption capability of the high-voltage interface switch and opening this switch.

The present invention relates to a superconducting nanowire single-photon detector, which can include a superconducting nanowire configured and arranged for the incidence of a photon on a region thereof and the formation, on that region, of a localized non-superconducting region or hotspot.

The superconducting nanowire is made of a high-Tc cuprate superconductor material having a superconducting critical temperature above 77 K.

The present invention also relates to a method for obtaining the superconducting nanowire single-photon detector of the present invention.

A photon source includes a photo-pair generator and a detection device. The photo-pair generator is configured to generate a photon-pair in receiving an input signal. A first photon of the photon-pair is output from the photon source via a first optical path. The detection device is configured to receive a second photon of the photon-pair. The detection device includes a transistor that has a semiconducting component that is a source and a drain of the transistor, and a superconducting component that is adjacent to the semiconducting component and is a gate of the transistor. The transistor is configured to transition from an off state to an on state in response a photon being incident upon the detection device.