The various embodiments described herein include methods, devices, and circuits for reducing or minimizing current crowding effects in manufactured superconductors. In some embodiments, a superconducting circuit includes: (1) a first component having a first connection point, the first connection point having a first width; (2) a second component having a second connection point, the second connection point having a second width that is larger than the first width; and (3) a connector electrically connecting the first connection point and the second connection point, the connector including: (a) a first taper having a first slope and a non-linear shape; (b) a second taper having a second slope; and (c) a connecting portion connecting the first taper to the second taper, the connecting portion having a third slope that is less than the first slope and less than the second slope.

A semiconductor-superconductor hybrid structure includes a semiconductor layer and a superconductor heterostructure on the semiconductor layer. The superconductor heterostructure includes a first superconductor layer on the semiconductor layer and a second superconductor layer on the first superconductor layer. The first superconductor layer comprises a first superconducting material and the second superconductor layer comprises a second superconducting material that is different from the first superconducting material. By providing the superconductor heterostructure as multiple layers of different superconducting materials, the superconducting and physical properties of the superconductor heterostructure can be improved compared to conventional superconducting homostructures, thereby increasing the performance of the semiconductor-superconductor hybrid structure.

An electronic device (e.g., a superconducting memory cell) includes a substrate and a layer of superconducting material disposed over the substrate. The layer of superconducting material is patterned to form a plurality of distinct instances of the layer of superconducting material including: a first wire; and a loop that is (i) distinct and separate from the first wire and (ii) capacitively coupled to the first wire while the loop and the first wire are in a superconducting state. The loop is configured to form a persistent current via the capacitive coupling in response to a write current applied to the first wire while the loop and the first wire are in the superconducting state. The persistent current represents a logic state of the electronic device.

Conventional readout of a superconducting nanowire single-photon detector (SNSPD) sets an upper bound on the output voltage to be the product of the bias current and the load impedance, I.sub.BZ.sub.load, where Z.sub.load is limited to 50 in standard RF electronics. This limit is broken/exceeded by interfacing the 50 load and the SNSPD using an integrated superconducting transmission line taper. The taper is a transformer that effectively loads the SNSPD with high impedance without latching. The taper increases the amplitude of the detector output while preserving the fast rising edge. Using a taper with a starting width of 500 nm, a 3.6 higher pulse amplitude, 3.7 faster slew rate, and 25.1 ps smaller timing jitter was observed. The taper also makes the detector's output voltage sensitive to the number of photon-induced hotspots and enables photon number resolution.

A quantum device includes: a substrate; and at least three co-planar structures arranged on a surface of the substrate, each co-planar structure, of the at least three co-planar structures, including a superconductor, in which a first effective dielectric constant between a first co-planar structure and a second co-planar structure that is a nearest neighbor to the first co-planar structure is above a first threshold, a second effective dielectric constant between the first co-planar structure and a third co-planar structure that is a next nearest neighbor to the first so-planar structure is less than a second threshold, and the second threshold is less than the first threshold.

The present disclosure relates to a method for manufacturing of specially designed substrates for growth of nanostructures and patterned growth on said nanostructures. The present disclosure further relates to nanostructures, in particular hybrid semiconductor nanostructures with patterned growth of superconducting material for use in quantum devices. The presently disclosed method can be utilized for in-situ manufacturing of quantum devices that have not been contaminated by ex-situ processes.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

This disclosure relates to Superconducting Quantum Interference Apparatuses, such as SQUID arrays and SQUIFs. A superconducting quantum interference apparatus comprises an array of loops each loop constituting a superconducting quantum interference device. The array comprises multiple columns, each of the columns comprises multiple rows connected in series, each of the multiple rows comprises a number of loops connected in parallel, and the number of loops connected in parallel in each row is more than two and less than 20 to improve a performance of the apparatus. It is an advantage that keeping the number of loops in parallel below 20 improves the performance of the apparatus. This is contrary to existing knowledge where it is commonly assumed that a larger number of parallel loops would increase performance.

The present invention provides a superconducting block, comprising, a pair of cores with materials that are electrically conductive in their normal states. The pair of cores are embedded in the shell with an intervening centroidal distance, with a material that is electrically conductive in its normal state. The embedded pair of cores and the shell are configured to be superconductive. The present invention also provides a superconducting nanocrystal with at least the superconducting block. The present invention also provides a superconductive device with at least the superconducting block and the superconducting nanocrystal. The present invention further provides a process for fabricating the superconducting block and superconducting crystal. The present invention provides superconductors (superconducting block, superconducting nanocrystals) that can be employed to attain superconductivity at high temperatures, corresponding to temperatures existing in the terrestrial ambient and even higher.

Under certain conditions, a fermion in a superconductor can separate in space into two parts known as Majorana zero modes, which are immune to decoherence from local noise sources and are attractive building blocks for quantum computers. Here we disclose a metal-based heterostructure platform to produce these Majorana zero modes which utilizes the surface states of certain metals in combination with a ferromagnetic insulator and a superconductor. This platform has the advantage of having a robust energy scale and the possibility of realizing complex circuit designs using lithographic methods. The Majorana zero modes are interrogated using planar tunnel junctions and electrostatic gates to selectively tunnel into designated pairs of Majorana zero modes. We give example of qubit designs and circuits that are particularly suitable for the metal-based heterostructures.