A semiconductor circuit, including a plurality of first devices and a plurality of second devices provided on the front surface of the main board, wherein each of the first device and the second device has a plurality of electrodes including a first main electrode and a second main electrode arranged on an upper surface, and the first main electrode and the second main electrode are connected to the front surface of the main board; each of the first devices has a first end side facing the second device; each of the second devices has a second end side facing the first device; a whole region between the first main electrode and the first end side in the first direction is a first region; and a whole region between the second main electrode and the second end side in the first direction is a second region.

A power semiconductor module according to an embodiment may include a first substrate, a power semiconductor device bonded to the first substrate, a second substrate bonded to the power semiconductor device, a heat dissipation post bonded to the second substrate, and a molding member surrounding the first substrate, the power semiconductor device, the second substrate, and the heat dissipation post. In addition, a top surface of the heat dissipation post may be exposed through the molding member. In addition, a height of a top surface of the heat dissipation post may be the same as a height of the top surface of the molding member. In addition, the heat dissipation post may vertically overlap the power semiconductor device.

A semiconductor device, including: a heat dissipation plate having a heat dissipation surface; a cooling module having a cooling surface, the cooling module being disposed so that the cooling surface faces the heat dissipation surface of the heat dissipation plate; and a bonding member provided between the heat dissipation surface and the cooling surface. The bonding member includes: a thermally conductive part that bonds the heat dissipation surface and the cooling surface, and an electrically conductive part that electrically connects the heat dissipation surface and the cooling surface.

A GaN/SiC cascode power device is formed with first and second transistor groups. The first transistor group has one or more low-voltage normally-off GaN high-electron-mobility transistors. The second group has one or more high-voltage normally-on SiC junction-field-effect transistors. A backbone layer mechanically supports respective transistors in the two transistor groups and provides electrical connectivity among the respective transistors. The backbone layer is formed by embedding a network of conductive traces on or within an insulating rigid layer. The respective transistors are mounted on the backbone layer and electrically connected via the network of conductive traces. Advantageously, bonding wires are absent in providing intra-connection between the two transistor groups. Undesirable interconnection inductances are considerably reduced such that switching loss and switching oscillation, both overstressing the power device during a switching process, are suppressed.

According to one embodiment, a semiconductor memory device includes a first stacked body and a second stacked body in a first region. The semiconductor memory device includes a first via contact electrode in a second region adjacent to the first region and having a height that is at least half or more of a height of the first stacked body in the stacking direction, and a second via contact electrode disposed on the first via contact electrode in the stacking direction and electrically connected to the first via contact electrode and having a height that is at least half or more of the height of the second stacked body in the stacking direction. A diameter of a surface of the second via contact electrode facing the first via contact electrode is greater than a diameter of a surface of the first via contact electrode facing the second via contact electrode.

Provided is a semiconductor device with a configuration capable of ensuring insulation properties between terminals having different potentials and arranged with an insulating layer interposed. The semiconductor device includes: a first terminal; a second terminal having a part opposed to the first terminal and another part provided with a first opening not opposed to the first terminal; and an insulating layer including a body part interposed between the first terminal and the second terminal opposed to each other and a first protrusion connected to the body part and inserted to the first opening.

A semiconductor device with a small circuit scale and reduced power consumption is provided. The semiconductor device includes first to fifth circuits. Each of the first to fourth circuits includes first and second cells, a sixth circuit, first and second current generation circuits, a first input terminal, and a second output terminal. The first circuit to the fourth circuit are electrically connected to each other in a ring, and the first circuit is electrically connected to the fifth circuit. In each of the first to fourth circuits, the first cell is electrically connected to the second cell through the first wiring, the first current generation circuit, and the third wiring, and is electrically connected to the first input terminal and the sixth circuit through the second wiring. The second cell is electrically connected to the first output terminal through the second current generation circuit. Note that the first current generation circuit functions as a current mirror circuit, and the second current generation circuit functions as an arithmetic circuit of a function system. The first cell performs an arithmetic operation of a product, and the second cell retains the result of the arithmetic operation.

An encapsulated semiconductor package is proposed, including a plurality of rivets, and a plurality of connection pins, each connection pin having a pin tip and a pin end, the plurality of rivets are disposed in the encapsulant of the encapsulated semiconductor package, each rivet having a first rivet end and a second rivet end, each rivet being electrically mounted with a first rivet end on a corresponding bond pad of the semiconductor package; each rivet includes a rivet cavity configured to receive the pin tip of the connection pin; the pin tip of the connection pin is configured as a press-fit pin tip having an outer diameter larger than an inner diameter of the rivet cavity and configured for friction-based engagement with the rivet cavity.