In an embodiment, a semiconductor device may include a plurality of first nanostructures. The plurality of first nanostructures extend between first source/drain regions. The semiconductor device may also include a plurality of second nanostructures over the plurality of first nanostructures. The plurality of second nanostructures extend between second source/drain regions. The device may furthermore include a first gate stack around the plurality of first nanostructures. The device may in addition include a second gate stack over the first gate stack and disposed around the plurality of second nanostructures. The device may moreover include a vertical interconnect structure extending through the first and second gate stacks. The device may also include a frontside contact electrically coupled to a frontside of the vertical interconnect structure and a backside contact electrically coupled to a backside of the vertical interconnect structure.

A semiconductor device includes first and second active patterns extending in a first direction, the second active pattern being spaced apart from the first active pattern in a vertical direction, a first gate structure on the first and second active patterns and extending in a second direction, a first cutting pattern spaced apart from the first and second active patterns in the second direction and cutting the first gate structure, and a via pattern spaced apart from the second active pattern. The second active pattern includes a first portion having a first width, and a second portion having a second width smaller than the first width in the second direction. The first cutting pattern includes first and second line portions, and a first protrusion between the first and second line portions that protrudes from the first line portion. The via pattern extends vertically through the first protrusion.

A semiconductor device may include a semiconductor substrate including first and second regions, a first gate structure on the first region, and a second gate structure on the second region. Each of the first and second gate structures may include a metal pattern, a high-k dielectric pattern between the semiconductor substrate and the metal pattern, and a work-function layer between the high-k dielectric pattern and the metal pattern. The work-function layer of the first gate structure may include a first metal element in the metal pattern of the first gate structure and a dipole material in the high-k dielectric pattern of the first gate structure, and the work-function layer and the high-k dielectric pattern in the second gate structure may include a metal oxide material. In the second gate structure, an oxygen content in the work-function layer may be higher than that in the high-k dielectric pattern.

Embodiments of the present disclosure provide a semiconductor device structure having vertically stacked complementary field effect transistors (CFETs). The CFETs are formed by bonding two substrates having semiconductor stacks formed thereon. A bonding structure is formed between the semiconductor stacks using wafer bonding technology. Embodiments of the resent disclosure enable the flexibility of choosing different N/P channel properties, provide a simple way to form the N/P channel isolation structure, and reduce potential leakage path and defects in stacked CFETs.

In a method of manufacturing a semiconductor device, a fin structure including a stacked layer of first semiconductor layers and second semiconductor layers is formed, an isolation insulating layer is formed so that the stacked layer are exposed from the isolation insulating layer, a sacrificial cladding layer is formed over at least sidewalls of the exposed stacked layer, a sacrificial gate electrode is formed over the exposed stacked layer, an interlayer dielectric layer is formed, the sacrificial gate electrode is partially recessed to leave a pillar of the remaining sacrificial gate electrode, the sacrificial cladding layer and the first semiconductor layers are removed, a gate dielectric layer wrapping around the second semiconductor layer and a gate electrode over the gate dielectric layer are formed, the pillar is removed, and one or more dielectric layers are formed in a gate space from which the pillar is removed.

A semiconductor device includes first and second transistors and a contact plug. The first transistor includes first channels, a first gate structure and a first source/drain layer. The first gate structure extends in a first direction, and covers upper and lower surfaces and opposite sidewalls in the first direction of the first channels. The first source/drain layer is at opposite sides of the first gate structure in a second direction. The second transistor includes second channels, a second gate structure and a second source/drain layer. The second gate structure extends in the second direction, and covers upper and lower surfaces and opposite sidewalls in the second direction of the second channels. The second source/drain layer is at opposite sides of the second gate structure in the first direction. The contact plug extends in the vertical direction and contacts an upper surface of the first source/drain layer.

An integrated circuit includes a transistor having a plurality of stacked channels each extending between the source/drain regions of the transistor. The transistor also includes a hard mask nanostructure above the highest channel and extending between the source/drain regions of the transistor. A gate dielectric and gate metals wrap around the channels and the hard mask nanostructure.

Techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

A semiconductor structure includes nanostructures vertically stacked above a substrate, a gate structure wrapping around at least one of the nanostructures, a gate spacer extending along a sidewall of the gate structure, a source/drain feature abutting the nanostructures, and inner spacers interposing the source/drain feature and the gate structure. The source/drain feature includes a first epitaxial layer and a second epitaxial layer. A dopant concentration in the first epitaxial layer is less than a dopant concentration of the second epitaxial layer. The first epitaxial layer separates the second epitaxial layer from the nanostructures. The first epitaxial layer has a straight sidewall extending continuously from a sidewall of a topmost one of the nanostructures to a sidewall of a bottommost one of the nanostructures.

Provided are multi-gate devices and methods for fabricating such devices. A method includes forming a first gate structure and a second gate structure, wherein the first gate structure and the second gate structure have different structural configurations; performing a single etching process on the first gate structure and second gate structure to simultaneously form openings of different depths; and forming isolation material in the openings.