A vertical stack of three-dimensional transistors, such as nanoribbon-based transistors, includes a stack of nanoribbons with independent gates around subsets of nanoribbons in the stack. In previous nanoribbon transistors, a gate electrode wraps around all of the semiconductor regions and spans the areas between adjacent semiconductor regions, thus electrically coupling the centers of the semiconductor regions. To achieve a stack of semiconductor regions with independent gates, adjacent nanoribbons in the stack may be set at different distances apart, or two or more sacrificial materials may be included when forming the stack of semiconductor materials and selectively etched when forming different gates.

In one embodiment, a complementary field effect transistor (CFET) device includes one or more metallization layers between stacked transistors.

Methods of forming a metal gate structure of a stacked multi-gate device are provided. A method according to the present disclosure includes depositing a titanium nitride (TiN) layer over a channel region that includes bottom channel layers and top channel layers, depositing a dummy fill layer to cover sidewalls of the bottom channel layers, after the depositing of the dummy fill layer, selectively forming a blocking layer over the TiN layer along sidewalls of the top channel layers, selectively removing the dummy fill layer to release the bottom channel layers, selectively depositing a first work function metal layer to wrap around each of the bottom channel layers, forming a gate isolation layer over a top surface of the first work function metal layer, removing the blocking layer, releasing the top channel layers, and selectively depositing a second work function metal layer to wrap around each of the top channel layers.

The present disclosure provides an integrated circuit (IC) structure in accordance with some embodiments. The IC structure includes a circuit structure having semiconductor devices formed on a first substrate, an interconnect structure over the semiconductor devices; and a thermal dissipation structure formed on a second substrate. The second substrate is boned to the circuit structure such that the thermal dissipation structure is interposed between the first and second substrates. The thermal dissipation structure includes a diamond-like carbon (DLC) layer. The DLC layer includes a bottom portion having large grain sizes and a top portion having fine DLC grain sizes.

Semiconductor structures and methods are provided. A semiconductor structure according to the present disclosure includes a substrate, a first semiconductor layer over the substrate, a second semiconductor layer over the first semiconductor layer and including a channel region sandwiched between a first source/drain region and a second source/drain region, a first plurality of nanostructures disposed over the channel region, a first leakage block layer over the first source/drain region, a second leakage block layer over the second source/drain region, a dielectric layer on the first leakage block layer, a first source/drain feature on the dielectric layer and in contact with first sidewalls of the first plurality of nanostructures, and a second source/drain feature disposed on the second leakage block layer and in contact with second sidewalls of the first plurality of nanostructures. The first leakage block layer and the second leakage block layer includes an undoped semiconductor material.

Methods and devices that include forming a first epitaxial region and a second epitaxial region above the first epitaxial region. An opening may be formed extending from the first region to the second region. And a liner layer is deposited on a sidewall and a bottom of the opening. A plasma treatment is performed on the liner layer, which can form a conditioned or passivated region of the first epitaxial region that may be maintained during the growth of additional epitaxial material on the second epitaxial region.

In a semiconductor integrated circuit device, a standard cell includes: an active region forming the channel, source, and drain of a transistor; and a first power line extending in the X direction. The first power line, formed on the back side of the transistor, has an overlap with the active region in planar view. A second power line extending in the Y direction is formed in an interconnect layer located below the first power line. The second power line is connected to the first power line through a via and has an overlap with the active region in planar view.

Semiconductor devices and methods of manufacture are presented. In embodiments a method of manufacturing the semiconductor device includes forming a fin from a plurality of semiconductor materials, depositing a dummy gate over the fin, depositing a plurality of spacers adjacent to the dummy gate, removing the dummy gate to form an opening adjacent to the plurality of spacers, widening the opening adjacent to a top surface of the plurality of spacers, after the widening, removing one of the plurality of semiconductor materials to form nanowires, and depositing a gate electrode around the nanowires.

The present disclosure provides a semiconductor device and a method of forming the same. The semiconductor device includes a fin-shape base protruding from a semiconductor substrate. A top surface of the semiconductor substrate is in a (100) crystal plane, and a top surface of the fin-shape base is in a (110) crystal plane. The semiconductor device also includes channel members disposed over the top surface of the fin-shape base, a gate structure wrapping around at least one of channel members, a gate spacer extending along a sidewall of the gate structure, a source/drain feature abutting the channel members, and a dopant-free epitaxial feature under the source/drain feature. A top surface of the source/drain feature is in a (110) crystal plane. A top surface of the dopant-free epitaxial feature is in a (110) crystal plane.

A three-dimensional semiconductor device may include a first active region, which includes a first channel pattern and a first source/drain pattern connected to each other, on a substrate, a second active region, which includes a second channel pattern and a second source/drain pattern connected to each other, on the first active region, a gate electrode on the first and second channel patterns, a bottom active contact electrically connected to the first source/drain pattern and extended from the first source/drain pattern in a first direction, a lower metal layer provided below the bottom active contact, the lower metal layer including bottom via patterns and bottom interconnection lines electrically connected to the bottom active contact, and a division structure electrically connected to at least one of the bottom via patterns. The division structure may include a division liner pattern and a connection metal pattern penetrating the same.