A method includes providing a substrate having an epitaxial stack of layers including a plurality of semiconductor channel layers interposed by a plurality of dummy layers. The substrate includes a first device region and a second device region. An etch process is performed to remove a first portion of the epitaxial stack of layers from the second device region to form a trench in the second device region. The removed first portion of the epitaxial stack of layers includes at least one semiconductor channel layer of the plurality of semiconductor channel layers. An epitaxial layer is formed within the trench in the second device region and over the second portion of the epitaxial stack of layers. A top surface of the epitaxial layer in the second device region is substantially level with a top surface of the epitaxial stack of layers in the first device region.

An integrated circuit device includes a fin-shaped active region. A pair of lower channel regions are disposed on the active region. A pair of upper channel regions are disposed on upper portions of the lower channel regions. A lower source/drain region is formed on the active region, contacting the pair of lower channel regions. An upper source/drain region is formed on the lower source/drain region, contacting the pair of upper channel regions. The upper source/drain region includes a first semiconductor pattern contacting side surfaces of the pair of upper channel regions, a second semiconductor pattern covering the first semiconductor pattern, and a third semiconductor pattern filled between the pair of upper gate portions, and covering the first semiconductor pattern and the second semiconductor pattern. A lowermost portion of a lower surface of the upper source/drain region is a part of a lower surface of the third semiconductor pattern.

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first channel structure positioned over a substrate, first source/drain (S/D) regions positioned on ends of the first channel structure, and a first gate structure disposed all around the first channel structure. The second transistor includes a second channel structure positioned over the first channel structure, second S/D regions positioned on ends of the second channel structure, and a second gate structure disposed all around the second channel structure. The second channel structure has a smaller dimension than the first channel structure in a horizontal direction substantially parallel to a working surface of the substrate.

A semiconductor structure includes a first field effect transistor including a first gate spacer having first laterally-straight bottom edges that coincide with top edges of first laterally-straight sidewalls of the first gate dielectric. The semiconductor structure further includes a second field effect transistor including a second gate dielectric that includes at least one discrete gate-dielectric opening that overlies a respective second active region, and a second gate spacer including a contoured portion that overlies and laterally surrounds a second gate electrode, and at least one horizontally-extending portion that overlies the second active region and including at least one discrete gate-spacer openings. The second field effect transistor may have a symmetric or non-symmetric configuration.

Provided is a semiconductor device including a power distribution network layer on a lower surface of a substrate, a gate electrode on the substrate, a first source/drain pattern and a second source/drain pattern on the substrate, the first and second source/drain patterns each including a first pattern and a second pattern spaced apart from each other with the gate electrode therebetween, a through via structure penetrating the substrate and extending along a direction perpendicular to an upper surface of the substrate, the through via structure connecting the power distribution network layer and the first pattern of the first source/drain pattern, and a rear surface power via extending from below the second pattern of the first source/drain pattern to below the second pattern of the second source/drain pattern.

In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a substrate, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure is etched thereby forming a source/drain space, ends of the first semiconductor layers is laterally etched, an insulating layer is formed on a sidewall of the source/drain space, the insulating layer is partially etched, thereby forming one or more inner spacers on an etched end face of each of one or more first semiconductor layers and leaving a part of the insulating layer as a remaining insulating layer, and a source/drain epitaxial layer is formed in the source/drain space. After the source/drain epitaxial layer is formed, an end face of at least one of the second semiconductor layers is covered by the remaining insulating layer.

In a disclosed Schmitt trigger, an input stage includes a first p-channel field effect transistor (PFET) and a second PFET, which are connected in series to a VDD rail, and a first n-channel field effect transistor (NFET) and a second NFET, which are connected in series between ground and the second PFET. An output stage includes additional FETs for hysteresis. The first PFET and first NFET are different from the other FETs and have a higher voltage rating. For example, the first PFET and first NFET can be buried oxide field effect transistors (BOXFETs) and the other FETs can be laterally diffused metal oxide semiconductor field effect transistors (LDMOSFETs)). Gates of the first PFET and first NFET are connected to an input node. Gates of the second PFET and NFET are connected to receive reference voltages to prevent safe operating area (SOA) violations and control trigger voltage levels.

Techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

A semiconductor structure includes nanostructures vertically stacked above a substrate, a gate structure wrapping around at least one of the nanostructures, a gate spacer extending along a sidewall of the gate structure, a source/drain feature abutting the nanostructures, and inner spacers interposing the source/drain feature and the gate structure. The source/drain feature includes a first epitaxial layer and a second epitaxial layer. A dopant concentration in the first epitaxial layer is less than a dopant concentration of the second epitaxial layer. The first epitaxial layer separates the second epitaxial layer from the nanostructures. The first epitaxial layer has a straight sidewall extending continuously from a sidewall of a topmost one of the nanostructures to a sidewall of a bottommost one of the nanostructures.

A semiconductor device includes: a substrate; source/drain patterns on the substrate; a channel pattern between the source/drain patterns, the channel pattern including a plurality of semiconductor patterns; a gate electrode between the plurality of semiconductor patterns; an upper separation structure extending in a first direction and spaced apart from the gate electrode in a second direction intersecting the first direction; a first backside separation structure penetrating the substrate below the gate electrode in a third direction intersecting the first direction and the second direction; and a second backside separation structure penetrating the substrate and overlapping the upper separation structure in the third direction.