Provided is a semiconductor device including a first active pattern and a second active pattern on a substrate, a first source/drain pattern and a first channel pattern on the first active pattern, a second source/drain pattern and a second channel pattern on the second active pattern, and a gate electrode crossing each of the first channel pattern and the second channel pattern. Along a horizontal extension direction of the gate electrode, a first width of an upper surface of the first channel pattern is greater than a second width of an upper surface of the second channel pattern, and an upper surface of the first source/drain pattern is located at a vertically higher level than the upper surface of the first channel pattern.

A semiconductor device includes an active pattern extending on a substrate in a first direction, channel patterns vertically stacked on the active pattern, a separation structure extending in a second direction and separating each of the active pattern and the channel patterns into first and second portions, a gate structure extending in the second direction and onto the first portions of the channel patterns, a separation pattern extending in the first direction, separating the first portions of the channel patterns into first and second channel patterns, and separating the gate structure into first and second gate structures, and a third gate structure extending in the second direction and onto the second portions of the channel patterns. The second portions of the channel patterns have a width greater than a sum of first and second widths of the first and second channel patterns, respectively.

A semiconductor device structure includes a gate structure formed over a substrate. The semiconductor device structure also includes a source/drain structure formed beside the gate structure. The semiconductor device structure further includes a contact structure formed over the source/drain structure. The semiconductor device structure also includes a first cap layer formed over the contact structure. The semiconductor device structure further includes a dielectric structure extending from a top surface of the first cap layer into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.

A semiconductor device includes a lower interlayer insulating layer and an active pattern thereon, wherein the active pattern extends in a first horizontal direction and is spaced apart from an upper surface of the lower interlayer insulating layer in a vertical direction; first nanosheets on the active pattern; second nanosheets spaced apart from the first nanosheets in the first horizontal direction on the active pattern; a first gate electrode extending in a second horizontal direction and extending around the first plurality of nanosheets; a capping layer on the first gate electrode; and an active cut on the lower interlayer insulating layer, wherein the active cut is spaced apart from the first gate electrode in the first horizontal direction, and an uppermost surface of the active cut is farther than an upper surface of the capping layer from the upper surface of the lower interlayer insulating layer.

A semiconductor device includes: active regions extending in a first direction on a substrate; a device isolation layer; gate structures intersecting the active regions and extending in a second direction; a plurality of channel layers on the active regions spaced apart from each other in a third direction and surrounded by the gate structures; first and second source/drain regions spaced apart from each other, the source/drain regions being connected to the plurality of channel layers and in recess regions on both sides of the gate structures; sidewall spacer layers on side surfaces of the source/drain regions; and a backside contact plug penetrating one of the active regions, and contacting a lower surface of the first source/drain region, wherein the active regions include a step region, and wherein the first active region extends onto side surfaces of at least an upper region of the backside contact plug in the second direction.

A semiconductor device includes: a base pattern; a first metal structure penetrating the base pattern in a first direction; at least one gate structure including a gate electrode disposed on the first metal structure in the first direction; a second metal structure penetrating the base pattern in the first direction and spaced adjacent to the first metal structure in a second direction intersecting the first direction; and a source/drain structure including at least one of a source electrode or a drain electrode disposed on the second metal structure in the first direction, wherein the first metal structure and the second metal structure are electrically separated from each other by a blocking film.

A semiconductor device includes a first lower epitaxial pattern on a side of a gate structure, wherein the first lower epitaxial pattern is connected to a lower active pattern; a first upper epitaxial pattern on another side of the gate structure, wherein the first upper epitaxial pattern is connected to an upper active pattern; a cut pattern that is spaced apart from the lower and upper active patterns, is adjacent the gate structure, and extends in a first direction; and a via structure connected to the first lower epitaxial pattern and the first upper epitaxial pattern in the cut pattern, wherein the via structure includes a first pillar part overlapping the first upper epitaxial pattern in a second direction, a second pillar part overlapping the first lower epitaxial pattern in the second direction, and a connecting part extending in the first direction to connect the first and second pillar parts.

Provided is an integrated circuit device including a plurality of semiconductor patterns having different widths. In order to minimize or reduce current leakage from a semiconductor pattern having a relatively small width to below a source/drain region, a lower thin film having a certain thickness may be selectively formed below the source/drain region corresponding to the narrow semiconductor pattern, thereby improving electrical reliability of the device. Also, provided is an integrated circuit device including a plurality of semiconductor patterns having different widths. In order to minimize or reduce current leakage from a semiconductor pattern having a relatively small width to below a source/drain region, a lower thin film may be selectively and thickly deposited below the source/drain region corresponding to the narrow semiconductor pattern, thereby improving electrical reliability of the device.

An integrated circuit device includes a stacked transistor structure on a substrate. The stacked transistor structure includes a first transistor and a second transistor stacked on the first transistor. Each of the first and second transistors includes a plurality of channel patterns that extend between source/drain regions in a first direction and are alternately stacked with gate patterns in a second direction. For at least one of the first and second transistors, respective lengths of the channel patterns, the gate patterns, and/or inner spacers at opposing ends of the gate patterns differ along the first direction. Related devices and fabrication methods are also discussed.

Provided is a semiconductor device which includes: a 1.sup.st field-effect transistor (FET) including a 1.sup.st source/drain pattern; a 2.sup.nd FET including a 2.sup.nd source/drain pattern, vertically above the 1.sup.st FET; a 1.sup.st side spacer on a right surface of the 1.sup.st source/drain pattern, the 1.sup.st side spacer comprising an isolation material; and a frontside contact structure on a right surface of the 2.sup.nd source/drain pattern and a right surface of the 1.sup.st side spacer, wherein the frontside contact structure is connected to the 2.sup.nd source/drain pattern and is isolated from the 1.sup.st source/drain pattern by the 1.sup.st side spacer.