An integrated circuit device includes a substrate having an active region defined by a device isolation film, a recess trench disposed in the active region, spaced apart from the device isolation film, and extending in a vertical direction from a main surface of the substrate towards an interior of the substrate, and a recess channel transistor including a gate electrode disposed within the recess trench, the recess channel transistor including a channel positioned along a surface of the recess trench, wherein each of the recess trench and the gate electrode has a closed-loop shape in a plan view.

In an embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, patterning the multi-layer stack and the semiconductor substrate to form a fin structure, the fin structure including alternating semiconductor nanostructures and dummy nanostructures, where a bottommost dummy nanostructure of the dummy nanostructures has a first thickness, where first dummy nanostructures of the dummy nanostructures are disposed above the bottommost dummy nanostructure, and each of the first dummy nanostructures has a second thickness that is smaller than the first thickness, forming source/drain recesses in the fin structure, etching sidewalls of the first dummy nanostructures and the bottommost dummy nanostructure in the source/drain recesses to form sidewall recesses, forming inner spacers in the sidewall recesses in the first dummy nanostructures and the bottommost dummy nanostructure, and replacing the first dummy nanostructures and the bottommost dummy nanostructure with a gate structure.

A transistor may include a gate structure on a substrate, the gate structure including a first gate dielectric pattern including a first metal oxide. A gate electrode includes a lower portion with a second metal oxide doped with tetravalent and pentavalent elements or with a metal oxynitride doped with the tetravalent and pentavalent elements. The gate electrode includes an upper portion on the lower portion with a metal doped with the tetravalent and pentavalent elements or a metal nitride doped with the tetravalent and pentavalent elements and a source/drain region at an upper portion of the substrate adjacent to the gate structure.

A semiconductor device includes a substrate, a first channel pattern on the substrate, the first channel pattern having a first width, a first gate electrode extending in a second direction, a first gate capping pattern on an upper surface of the first gate electrode, a second channel pattern spaced apart from the first channel pattern, the first channel pattern having a second width, a second gate electrode extending in the second direction on the second channel pattern, a second gate capping pattern on an upper surface of the second gate electrode, a source/drain pattern on at least one side of the second channel pattern, a first source/drain contact connected to the source/drain pattern, a second source/drain contact spaced apart from the first source/drain contact, and a contact isolation film between the first source/drain contact and the second source/drain contact. The second width is greater than the first width.

A semiconductor device includes a substrate; an active region on the substrate and extending in a first direction; a device isolation film around the active region in the substrate; a first gate electrode extending on the active region in a second direction that intersects the first direction; a second gate electrode extending on the active region in the second direction and spaced apart from the first gate electrode in the first direction; a first connection gate electrode extending in the first direction and connected to a first end of the first gate electrode and a first end of the second gate electrode; and a source/drain region in the active region at a side of the first gate electrode.

An isolation structure for an N epitaxy-based silicon carbide device, and an N epitaxy-based silicon carbide high and low voltage integrated device and a preparation method therefor are provided. The isolation structure includes N-type substrate, a first isolation trench and a second isolation trench to form a high-voltage region, a low-voltage region and a level shift region, a second P-type doped region is arranged at the bottom of the low-voltage region and of the level shift region, a second N-type doped region is arranged on the second P-type doped region in the low-voltage region, and back-to-back PN junctions are formed by the N-type drift region, the second P-type doped region in the low-voltage region, and the second N-type doped region. A DMOS device is arranged in a high-voltage region, low-voltage devices are arranged in a low-voltage region, and an LDMOS device is arranged in a level shift region.