The disclosure relates to a simulation method for selecting an optimal composition ratio of an oxide semiconductor. The oxide semiconductor includes at least two elements selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), tin (Sn), silver (Ag), aluminum (Al), cadmium (Cd), magnesium (Mg), antimony (Sb), silicon (Si), titanium (Ti), and zirconium (Zr); oxygen (O); and inevitable impurities. The simulation method includes setting a simulation target composition ratio set including various composition ratios of elements constituting the oxide semiconductor, checking whether the oxide semiconductor satisfies Formulas 1, 2, and 3 for each of the various composition ratios included in the simulation target composition ratio set, and selecting a composition ratio satisfying Formulas 1, 2, and 3 as an optimal composition ratio. Formulas 1, 2, and 3 may be the same as described in the specification.

The n/p MOS gate stack includes a semiconductor substrate having an nMOS region and a pMOS region, an nMOS stack including a first interface layer, a first high dielectric layer formed on the first interface layer, a first n-metal layer formed on the first high dielectric layer, and a first upper electrode formed on the first n-metal layer, which are formed in the nMOS region, and a pMOS stack including a second interface layer, a second high dielectric layer formed on the second interface layer, a second p-metal layer formed on the second high dielectric layer, a second n-metal layer formed on the second p-metal layer, and a second upper electrode formed on the second n-metal layer, which are formed in the pMOS region. The first high dielectric layer includes a first dipole material, and the second p-metal layer includes a second dipole material.

Provided is a flash memory device including a first gate electrode including a semiconductor material, a tunnel insulating pattern in contact with an upper surface of the first gate electrode, a charge trapping pattern on the tunnel insulating pattern, a blocking pattern on the charge trapping pattern, a channel on the blocking pattern, the channel including an oxide semiconductor material, source/drain patterns on the channel, the source/drain patterns being spaced apart from each other, and a second gate electrode in contact with the channel, the second gate electrode being between adjacent source/drain patterns of the source/drain patterns.

Provided are a semiconductor device and manufacturing method therefor, and a three-dimensional dynamic random access memory. The semiconductor device includes: a substrate; channel structures, arranged on the substrate along a first direction; bit lines, each arranged between one of the channel structures and the substrate and electrically connected to the channel structure, and extending along a second direction; and word lines, each arranged on at least one side of the channel structure and extending along a third direction, where the first direction intersects with the substrate, the second direction is parallel to the substrate, and the third direction is parallel to the substrate and intersects with the second direction; and the channel structure includes a filling material and an oxide semiconductor layer arranged on an outer surface of the filling material.

A Schottky barrier diode includes an anode electrode which is brought into Schottky contact with a drift layer, a cathode electrode which is brought into ohmic contact with a semiconductor substrate, an insulating film covering the inner wall of a trench formed in the drift layer, a metal film covering the inner wall of the trench through the insulating film and electrically connected to the anode electrode, and a field insulating layer. The field insulating layer includes a first part positioned between an upper surface of the drift layer and the anode electrode and a second part covering the inner wall of the trench through the metal film and insulating film. With this configuration, even when misalignment occurs between the trench and the field insulating layer, dielectric breakdown can be prevented.

A multilayer structure of the present invention is a multilayer structure including a base substrate and a semiconductor film that is made of -Ga.sub.2O.sub.3 or an -Ga.sub.2O.sub.3-based solid solution and has a corundum crystal structure, the semiconductor film being disposed on the base substrate. The semiconductor film has an average film thickness of greater than or equal to 10 m. The semiconductor film is convexly or concavely warped. An amount of warpage of the semiconductor film is 20 m or greater and 64 m or less.

Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes an oxide semiconductor layer including a plurality of metals, wherein, with respect to the plurality of metals, a content of indium (In) is less than 50 at %, and a content of zinc (Zn) is 0 at %, a gate electrode being apart from the oxide semiconductor layer, a gate insulating layer being between the oxide semiconductor layer and the gate electrode, and a first electrode and a second electrode on the oxide semiconductor layer and being apart from each other with the gate electrode interposed therebetween.

Group III oxide semiconducting devices with effective device isolation and edge termination regions.

The present disclosure relates to an oxide semiconductor memory device and a manufacturing method thereof, and more particularly, to an oxide semiconductor memory device forming an amorphous indium-gallium-zinc-oxide (hereinafter, referred to as a-IGZO) thin film and a manufacturing method thereof. The present disclosure is to solve a problem of oxide semiconductor forming an a-IGZO thin film having a negative threshold voltage and improve mobility characteristics.

A Schottky barrier diode, including a first n-type semiconductor layer including a -Ga.sub.2O.sub.3-based single crystal epitaxial layer and having a first carrier concentration that determines reverse breakdown voltage and forward voltage, a second n-type semiconductor layer including a -Ga.sub.2O.sub.3-based single crystal substrate and having a second carrier concentration that is higher than the first carrier concentration and determines forward voltage, a Schottky electrode provided on a surface of the first n-type semiconductor layer on the opposite side to the second n-type semiconductor layer, and an ohmic electrode provided on a surface of the second n-type semiconductor layer on the opposite side to the first n-type semiconductor layer. The -Ga.sub.2O.sub.3-based single crystal substrate includes a surface that has a plane orientation rotated by an angle of not more than 37.5 from a (010) plane.