Embodiments of the present disclosure provide a semiconductor device structure and methods of forming the same. The method includes forming a fin structure from a substrate, and the fin structure includes a plurality of semiconductor layers. The method further includes depositing a gate dielectric layer around a portion of each semiconductor layer of the plurality of semiconductor layers, depositing an adhesion layer on the gate dielectric layer, and the adhesion layer surrounds the portion of each semiconductor layer of the plurality of semiconductor layers. The method further includes depositing a fluorine-containing layer on the adhesion layer, and the fluorine-containing layer surrounds the portion of each semiconductor layer of the plurality of semiconductor layers. The method further includes performing an annealing process on the fluorine-containing layer, removing the fluorine-containing layer and the adhesion layer, and forming a gate electrode layer on the gate dielectric layer.

The transistor includes a gate structure on a substrate, and a source/drain region at an upper portion of the substrate adjacent to the gate structure and containing n-type impurities. The gate structure may include a gate interface pattern; a first gate dielectric pattern on the gate interface pattern and containing a compound of a first metal, wherein a dielectric constant of the compound of the first metal is greater than a dielectric constant of silicon oxide; a second gate dielectric pattern on the first gate dielectric pattern and containing an oxide or an oxynitride of a second metal different from the first metal, wherein an upper portion of the second gate dielectric pattern is doped with carbon of a first concentration; and a gate electrode on the second gate dielectric pattern.

The semiconductor device includes a substrate including a first area having a first surface and a second area having a second surface, wherein a vertical level of the first surface is different from a vertical level of the second surface; a first gate structure disposed on the first area, wherein the first gate structure includes a first gate insulating film and a first gate electrode layer disposed on the first gate insulating film; a second gate structure disposed on the second area, wherein the second gate structure includes a second gate insulating film, and a second gate electrode layer disposed on the second gate insulating film, wherein the second gate electrode layer includes first and second polysilicon layers on the second gate insulating film, wherein the first polysilicon layer is disposed between the first surface and the second surface, and the second polysilicon layer is disposed higher the first surface.

Embodiments of the invention include forming a first transistor having first nanosheets, first dipole gate dielectric material being formed around the first nanosheets. An aspect includes forming a second transistor comprising second nanosheets, second dipole gate dielectric material being formed around the second nanosheets, the first and second transistors being in a vertical stack, a first spacing between the first nanosheets being different from a second spacing between the second nanosheets. An aspect includes forming a workfunction metal stack having a first workfunction metal and a second workfunction metal, the first and second workfunction metals being formed between the first nanosheets, the first workfunction metal being formed to pinch off in the second spacing between the second nanosheets such that the second workfunction metal is absent in the second spacing between the second nanosheets.

Multiple threshold voltage (Multi-V.sub.t) integration schemes for semiconductor devices are described. The methods include the use of diffusion barrier layers configured to provide multi-V.sub.t through controlled dopant diffusion.

A semiconductor device includes a first substrate, a first active pattern including a first lower pattern and a plurality of first sheet patterns, a first gate structure surrounding the plurality of first sheet patterns, a first high-k insulating film disposed between the first gate structure and the plurality of first sheet patterns, a first gate insulating film disposed between the plurality of first sheet patterns and the first high-k insulating film, a plurality of second sheet patterns, a second gate structure surrounding the plurality of second sheet patterns, and a second high-k insulating film disposed between the second gate structure and the plurality of second sheet patterns, wherein the first high-k insulating film includes a first dopant, the second high-k insulating film includes a second dopant different from the first dopant, and the second dopant includes at least one of silicon, aluminum, zirconium, yttrium, scandium, nitrogen, gadolinium, and germanium.