The present disclosure relates to a manufacturing method for a power semiconductor device (1, 40), comprising: forming multiple growth templates on a carrier substrate (2), comprising at least a first plurality of hollow growth templates (18) and a second plurality of hollow growth templates (28); selectively growing a first sequence of differently doped wide bandgap semiconductor materials in each one of the first hollow growth templates (18), thereby forming a corresponding plurality of first semiconductor structures (5) of a first type, in particular n+/p/n/n+ structures; and selectively growing a second sequence of differently doped wide bandgap semiconductor materials in each one of the second hollow growth templates (28), thereby forming a corresponding plurality of second semiconductor structures (6) of a second type, in particular n+/n/p/n+ structures. The disclosure further relates to a power semiconductor device (1, 40) comprising a carrier substrate (2), at least one dielectric layer (4, 27, 31), a plurality of first semiconductor structures (5) of a first type, and a plurality of second semiconductor structures (6) of a second type formed within the at least one dielectric layer (4, 27, 31).

An integrated circuit device includes a hammer-shaped sheet separation wall between nanosheet stack structures, thereby improving a patterning margin of a gate electrode and preventing or reducing an effective channel width from being decreased. That is, the integrated circuit device may provide increased stable performance and improved reliability in a nanosheet field-effect transistor.

A semiconductor device includes a substrate, an active pattern extending in a first direction on the substrate, a plurality of lower nanosheets stacked on the active pattern and spaced apart from each other in a vertical direction, a nanosheet isolation layer including an insulating material on an upper surface of an uppermost nanosheet of the plurality of lower nanosheets, a plurality of upper nanosheets stacked on an upper surface of the nanosheet isolation layer and spaced apart from each other in the vertical direction, a gate electrode extending in a second direction different from the first direction on the active pattern, the gate electrode extending on the plurality of lower nanosheets, the nanosheet isolation layer, and the plurality of upper nanosheets, and an inner spacer on opposing sidewalls of the gate electrode between either adjacent ones of the upper nanosheets, or adjacent ones of the lower nanosheets.

A semiconductor device may include a first active pattern on a substrate, channel patterns on the first active pattern, a gate electrode extending in a first direction on the first active pattern, and a backbone structure extending in a second direction intersecting the first direction. The first active pattern includes a first region and a second region spaced apart in the second direction, the first active pattern includes a first active sidewall in direct contact with the backbone structure and a second active sidewall spaced apart from the first active sidewall in the first direction, and a distance between the first active sidewall and the second active sidewall in the first direction varies as the first active pattern extends from the first region toward the second region.

The present disclosure provides a semiconductor device and a fabricating method thereof, including a source structure, a drain structure, a gate structure, a channel structure, a supporting layer and a gate dielectric layer. The source structure and the drain structure are stacked in a vertical direction, and the gate structure is disposed between the drain structure and the source structure. The channel structure is partially disposed in the gate structure and is connected the drain structure and the source structure. The supporting layer is disposed on a sidewall of the channel structure. The gate dielectric layer is partially disposed between the channel structure and the gate structure in a horizontal direction, and partially disposed between the supporting layer and the gate structure. Through the arrangement of the supporting layer, the channel length of the semiconductor device will be effectively shrunken, to improve the performance and operation of the semiconductor device.

A semiconductor device includes active patterns spaced apart from one another in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern on the active patterns, in which the lower channel pattern and the lower source/drain pattern are alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern on the active patterns and on the lower channel pattern and the upper channel pattern; and a gate inner spacer on the gate pattern, and between the lower source/drain pattern and the upper source/drain pattern.

In an embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, patterning the multi-layer stack and the semiconductor substrate to form a fin structure, the fin structure including alternating semiconductor nanostructures and dummy nanostructures, where a bottommost dummy nanostructure of the dummy nanostructures has a first thickness, where first dummy nanostructures of the dummy nanostructures are disposed above the bottommost dummy nanostructure, and each of the first dummy nanostructures has a second thickness that is smaller than the first thickness, forming source/drain recesses in the fin structure, etching sidewalls of the first dummy nanostructures and the bottommost dummy nanostructure in the source/drain recesses to form sidewall recesses, forming inner spacers in the sidewall recesses in the first dummy nanostructures and the bottommost dummy nanostructure, and replacing the first dummy nanostructures and the bottommost dummy nanostructure with a gate structure.

A method for manufacturing a co-integrated semiconductor structure from a first and a second layer stack is provided. The first layer stack includes a channel layer and a sub-stack. Each sub-stack includes a sacrificial layer of a first type, a first slender layer on the sacrificial layer of the first type, a sacrificial layer of a second type, a second slender layer, a further sacrificial layer of the first type, and a further channel layer on the further sacrificial layer of the first type. The second layer stack includes a channel layer and a sub-stack. Each sub-stack includes a sacrificial layer of the first type and a further channel layer on the sacrificial layer of the first type. A separation between the neighboring channel layers of the first layer stack is larger than a separation between neighboring channel layers of the second layer stack.

Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate along a first direction, and a plurality of second nanostructures formed adjacent to the first nanostructures. The semiconductor structure includes a first gate structure formed on the first nanostructures along a second direction, and the first gate structure includes a first gate dielectric layer. The semiconductor structure includes a second gate structure formed on the second nanostructures. The semiconductor structure includes a dielectric wall structure between the first gate structure and the second gate structure along the first direction. The dielectric wall structure has a top portion and a bottom portion, and the bottom portion is wider than the top portion.