A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1.sup.st cell and a 2.sup.nd cell placed next to each other in a cell width direction, wherein the 1.sup.st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1.sup.st cell, and connects a vertical field-effect transistor (VFET) of the 1.sup.st cell to a power rail of the 1.sup.st cell, wherein a 2.sup.nd cell includes a connector connected to a power rail of the 2.sup.nd cell, wherein the fin of the 1.sup.st cell and the connector of the 2.sup.nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1.sup.st cell and the connector of the 2.sup.nd cell are merged.

The present disclosure provides a semiconductor device and a fabricating method thereof, including a source structure, a drain structure, a gate structure, a channel structure, a supporting layer and a gate dielectric layer. The source structure and the drain structure are stacked in a vertical direction, and the gate structure is disposed between the drain structure and the source structure. The channel structure is partially disposed in the gate structure and is connected the drain structure and the source structure. The supporting layer is disposed on a sidewall of the channel structure. The gate dielectric layer is partially disposed between the channel structure and the gate structure in a horizontal direction, and partially disposed between the supporting layer and the gate structure. Through the arrangement of the supporting layer, the channel length of the semiconductor device will be effectively shrunken, to improve the performance and operation of the semiconductor device.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

Methods of fabricating a 3D semiconductor device including: forming a first level including a first single crystal layer and first transistors, includes a single crystal channel; forming a first metal layer in the first level and a second metal layer overlaying the first metal layer; forming memory control circuits in the first level; forming a second level including second transistors, where at least one of the second transistors includes a metal gate; forming a third level including third transistors; forming a fourth level including fourth transistors, where the second level includes first memory cells, where the fourth level includes second memory cells, where the memory control circuits include control of data written into the first memory cells and into the second memory cells, where at least one of the transistors includes a hafnium oxide gate dielectric.

A three-terminal 2T0C memory cell is formed based on a dual-gate transistor. A second transistor used as a read transistor is disposed as the dual-gate transistor. A first control electrode of the second transistor is configured to store written data during a write operation, and a second control electrode of the second transistor is configured to control a current path between a bit line and a read word line. During the write operation, a cut-off voltage may be loaded to the read word line connected to the second control electrode of the second transistor, to control the second transistor to be turned off, and the current path between the bit line and the read word line may be blocked during the write operation. In comparison with a four-terminal 2T0C memory cell, complexity and an area of SA routing are reduced, and storage density can be effectively improved.