A module (100) includes a package substrate (170) for receiving a flip chip-attached semiconductor chip. A first flip chip-attached semiconductor chip (140) is attached to the package substrate (170) and a first ball grid array-attached packaged semiconductor chip (110) is attached to the package substrate (170). The first flip chip-attached semiconductor chip (140) and the first ball grid array-attached semiconductor chip (110) are in electrical communication with each other. The module (100) includes a connection component (160) attached to the package substrate (170). The connection component (160) includes an electrical coupling to couple the package substrate (170) to a corresponding connection component (160) on a motherboard (400). The package substrate (170) includes multiple conductive lines (177) to couple the first flip chip-attached semiconductor chip (140) to the first ball grid array-attached semiconductor chip (110) and to the connection component (160) attached to the package substrate (170).

A module (100) includes a package substrate (170) for receiving a flip chip-attached semiconductor chip. A first flip chip-attached semiconductor chip (140) is attached to the package substrate (170) and a first ball grid array-attached packaged semiconductor chip (110) is attached to the package substrate (170). The first flip chip-attached semiconductor chip (140) and the first ball grid array-attached semiconductor chip (110) are in electrical communication with each other. The module (100) includes a connection component (160) attached to the package substrate (170). The connection component (160) includes an electrical coupling to couple the package substrate (170) to a corresponding connection component (160) on a motherboard (400). The package substrate (170) includes multiple conductive lines (177) to couple the first flip chip-attached semiconductor chip (140) to the first ball grid array-attached semiconductor chip (110) and to the connection component (160) attached to the package substrate (170).

Integrated circuit packages with stiffeners containing semiconductor dies and associated methods are disclosed. An example apparatus includes: a base die coupled to a package substrate; a stiffener adjacent the base die, the stiffener including a cavity; and a semiconductor die different from the base die. The semiconductor die is in the cavity in the stiffener. The example apparatus also includes a bridge to electrically couple the semiconductor die to the base die.

A 3D semiconductor memory device includes a peripheral circuit structure, an intermediate insulating layer and a cell array structure. The cell array structure includes a first substrate including a cell array region and a connection region; a stack structure comprising electrode layers and electrode interlayer insulating layers alternately stacked on the first substrate; a planarization insulating layer covering an end portion of the stack structure on the connection region; and a first through-via penetrating the planarization insulating layer, the first substrate and the intermediate insulating layer. The first through-via connects one of the electrode layers to the peripheral circuit structure. The first through-via includes a first and second via portion integrally connected to each other. The first via portion penetrates the planarization insulating layer and has a first width. The second via portion penetrates the intermediate insulating layer and has a second width greater than the first width.

A 3D semiconductor memory device includes a peripheral circuit structure, an intermediate insulating layer and a cell array structure. The cell array structure includes a first substrate including a cell array region and a connection region; a stack structure comprising electrode layers and electrode interlayer insulating layers alternately stacked on the first substrate; a planarization insulating layer covering an end portion of the stack structure on the connection region; and a first through-via penetrating the planarization insulating layer, the first substrate and the intermediate insulating layer. The first through-via connects one of the electrode layers to the peripheral circuit structure. The first through-via includes a first and second via portion integrally connected to each other. The first via portion penetrates the planarization insulating layer and has a first width. The second via portion penetrates the intermediate insulating layer and has a second width greater than the first width.

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller under the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit disposed over and electrically connected to the memory controller, and a packaging substrate under and electrically connected to the memory controller. A die area of the memory controller is larger than the sum of a horizontal cross-section area of the memory stack and a die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV in each semiconductor die.

An IC structure includes a memory stack including semiconductor dies horizontally separate with each other, wherein each semiconductor die has a top surface, a bottom surface, four sidewalls, and a plurality of edge pads arranged along a sidewall. The IC structure further includes a memory controller under the first memory stack and electrically connected to the edge pads of each semiconductor die, a processor circuit disposed over and electrically connected to the memory controller, and a packaging substrate under and electrically connected to the memory controller. A die area of the memory controller is larger than the sum of a horizontal cross-section area of the memory stack and a die area of the processor circuit. There is no interposer between the packaging substrate and the memory controller, and there is no TSV in each semiconductor die.

Disclosed herein is a semiconductor module that includes a substrate body including first to third insulating layers, and a semiconductor IC having a main surface on which a redistribution layer is provided and a back surface partially covered with a back surface conductor. The semiconductor IC is embedded in the first insulating layer such that the main surface faces the second insulating layer side, and that the back surface faces the third insulating layer side. The thermal expansion coefficient of the redistribution layer is smaller than the thermal expansion coefficient of the back surface conductor. The thermal expansion coefficient of the second insulating layer is larger than the thermal expansion coefficient of the third insulating layer.

Disclosed herein is a semiconductor module that includes a substrate body including first to third insulating layers, and a semiconductor IC having a main surface on which a redistribution layer is provided and a back surface partially covered with a back surface conductor. The semiconductor IC is embedded in the first insulating layer such that the main surface faces the second insulating layer side, and that the back surface faces the third insulating layer side. The thermal expansion coefficient of the redistribution layer is smaller than the thermal expansion coefficient of the back surface conductor. The thermal expansion coefficient of the second insulating layer is larger than the thermal expansion coefficient of the third insulating layer.

Methods, systems, and devices for front-to-front bonding in a stacked memory system are described. The stacked memory system may include a package substrate and a volatile memory die with a front side. The stacked memory system may also include a logic die with a front side that is bonded with the front side of the volatile memory die. The back side of the stacked memory system may be coupled with a conductive bump that in turn is coupled with the package substrate.