The present disclosure provides a chip package structure and a fabrication method thereof, a memory system, and an electronic apparatus, and relates to the field of chip package technology. The chip package structure includes a stack structure and at least one first conductive pillar. The stack structure includes a plurality of semiconductor structures that are stacked. The stack structure includes a first surface and a second surface that are opposite in a stacking direction. The first conductive pillar extends along the stacking direction from the first surface of the stack structure, penetrates through at least one of the semiconductor structures, and is connected to one of the semiconductor structures. The above-mentioned chip package structure may be applied in a memory system to realize read and write operations of data.

A semiconductor package includes a first redistribution layer (RDL) including a first redistribution wiring structure, a first semiconductor chip on the first RDL and electrically connected to the first redistribution wiring structure, a molding layer on the first RDL and covering the first semiconductor chip and having one or more surfaces at least partially defining a recess at an upper surface of the molding layer, a planarization layer contacting the upper surface of the molding layer and having a flat upper surface, and a second redistribution layer (RDL) on the planarization layer and including a second redistribution wiring structure. The upper surface of the molding layer and a lower surface of the planarization layer collectively at least partially define a void between the upper surface of the molding layer and the lower surface of the planarization layer.

Disclosed is a semiconductor package comprising a first redistribution substrate, first and second semiconductor chips mounted on a top surface of the first redistribution substrate and horizontally spaced apart, a molding layer disposed on the top surface of the first redistribution substrate and surrounding the first and second semiconductor chips, a second redistribution substrate disposed on a top surface if the molding layer, an upper package mounted on a top surface of the second redistribution substrate, a vertical electrical connection structure disposed on one side of the first and second semiconductor chips and connecting the first redistribution substrate to the second redistribution substrate, a plurality of external connection terminals disposed on a bottom surface of the first redistribution substrate, and a bridge chip and a capacitor chip that are mounted on the bottom surface of the first redistribution substrate.

Disclosed is a semiconductor package comprising a first redistribution substrate, first and second semiconductor chips mounted on a top surface of the first redistribution substrate and horizontally spaced apart, a molding layer disposed on the top surface of the first redistribution substrate and surrounding the first and second semiconductor chips, a second redistribution substrate disposed on a top surface if the molding layer, an upper package mounted on a top surface of the second redistribution substrate, a vertical electrical connection structure disposed on one side of the first and second semiconductor chips and connecting the first redistribution substrate to the second redistribution substrate, a plurality of external connection terminals disposed on a bottom surface of the first redistribution substrate, and a bridge chip and a capacitor chip that are mounted on the bottom surface of the first redistribution substrate.

Disclosed herein are methods, systems and devices including a first layer with a first compute device, a second compute device, and a first connecting element, while a second layer has a first support circuit. The first compute device is configured to electrically connect to the second compute device via the first support circuit and the first connecting element. In some embodiments, the first support circuit includes a power layer on a first side of the support circuit, and the first support circuit may include a signal network layer on a second side of the first support circuit, the second side opposite the first side.

Disclosed herein are methods, systems and devices including a first layer with a first compute device, a second compute device, and a first connecting element, while a second layer has a first support circuit. The first compute device is configured to electrically connect to the second compute device via the first support circuit and the first connecting element. In some embodiments, the first support circuit includes a power layer on a first side of the support circuit, and the first support circuit may include a signal network layer on a second side of the first support circuit, the second side opposite the first side.

A method for manufacturing a heterogenous reconstructed wafer is provided. The method includes bonding a plurality of previously-tested main dies to a side of a silicon carrier wafer. The method also includes bonding a plurality of support dies to the side of the silicon carrier wafer such that the plurality of support dies is disposed in gaps between the plurality of main dies. The method also includes filling gaps between the plurality of main dies and the plurality of support dies with a gap-fill material such that the gap-fill material forms a gap-fill layer around and above each of the plurality of main dies and each of the plurality of support dies. The method then includes removing the silicon carrier wafer to form a heterogenous reconstructed wafer.

A method for manufacturing a heterogenous reconstructed wafer is provided. The method includes bonding a plurality of previously-tested main dies to a side of a silicon carrier wafer. The method also includes bonding a plurality of support dies to the side of the silicon carrier wafer such that the plurality of support dies is disposed in gaps between the plurality of main dies. The method also includes filling gaps between the plurality of main dies and the plurality of support dies with a gap-fill material such that the gap-fill material forms a gap-fill layer around and above each of the plurality of main dies and each of the plurality of support dies. The method then includes removing the silicon carrier wafer to form a heterogenous reconstructed wafer.

A semiconductor power device is described, having: a package; a power die arranged within the package and integrating a power structure that generates a load electric current designed to be supplied to an electric load. The device is also provided, within the package, with: at least a first conductive path designed to be flown through by a first sensing current, which is a function of the load electric current; and a current sensor with magnetic-based operation, integrated into a sensor die coupled to the first conductive path and which generates a current sensing signal on the basis of the first sensing current and indicative of the load electric current.

Disclosed are a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes a plurality of chiplet substrate units disposed spaced apart from each other or adjacent to each other, each of the chiplet substrate units having a plurality of via-type wiring elements, each of the chiplet substrate units including at least one of one or more passive device elements and one or more active device elements, a molding layer configured to form a single substrate shape along with the chiplet substrate units while filling spaces between and around the chiplet substrate units and to expose the chiplet substrate units, a redistribution layer member disposed on a first surface of a package substrate including the chiplet substrate units and the molding layer, and a plurality of chips mounted on the redistribution layer member so as to be electrically connected to the redistribution layer member.