A manufacturing method of a semiconductor device includes patterning an ion implantation mask above a second conductivity type semiconductor layer, and forming first conductivity type columns and second conductivity type columns within the second conductivity type semiconductor layer by implanting first conductivity type impurity ions into the second conductivity type semiconductor layer through openings in the ion implantation mask. The patterning the ion implantation mask includes forming a mask forming layer above the second conductivity type semiconductor layer, forming grooves extending from an upper surface of the mask forming layer toward the second conductivity type semiconductor layer, embedding a shielding portion containing metal into the grooves, and removing the mask forming layer located between the shielding portion to form the openings.

A semiconductor device, including: a semiconductor substrate made of silicon carbide; a parallel pn layer having a plurality of first-conductivity-type regions and a plurality of second-conductivity-type regions repeatedly alternating each other; a first semiconductor region between a first main surface of the semiconductor substrate and the parallel pn layer; a plurality of second semiconductor regions between the first main surface and the first semiconductor region; a plurality of trenches penetrating through the second semiconductor regions, respectively, and through the first semiconductor region, and reaching the parallel pn layer; a plurality of gate electrodes provided in the plurality of trenches via a plurality of gate insulating films; a first electrode electrically connected to the first semiconductor region and the second semiconductor regions; and a second electrode provided at a second main surface of the semiconductor substrate. The first semiconductor region intersects with the second-conductivity-type regions at a plurality of intersecting portions.

A radiation-hardened silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) device structure and a preparation method thereof, comprising an N.sup. drift layer, an N.sup.+ substrate layer is arranged beneath the N.sup. drift layer, a carrier storage layer is arranged above the N.sup. drift layer, a source metal layer is arranged above the carrier storage layer, a junction field-effect transistor (JFET) region is arranged in a middle beneath the source metal layer, a trench is introduced inside the JFET region, an interior of the trench is provided with a P-type doped region and a filling region, P-base regions are arranged on both sides of the trench, N.sup.+ source regions and P.sup.+ regions are arranged in the P-base regions. The invention significantly reduces electric field strength in the thin gate oxide, thereby enhancing the single-event gate rupture immunity of the device.

A semiconductor device includes a voltage sustaining layer of a first conductivity type and a superjunction layer disposed in contact with an upper surface of the voltage sustaining layer. The superjunction layer includes first regions of the first conductivity type and second regions of a second conductivity type alternately arranged along a first direction. Each of the second regions includes a lower second region in contact with the voltage sustaining layer and an upper second region disposed in contact with an upper surface of the lower second region. A lower maximum width that is a maximum width in the first direction of the lower second region is greater than an upper maximum width that is a maximum width in the first direction of the upper second region. A density of fixed charges during depletion is higher in the lower second region than in the upper second region.