A semiconductor device including a gate structure including a gate electrode which is formed over a substrate and includes a metal whose volume is increased when solidified, and a gate spacer formed on both sides of the gate structure. The performance of semiconductor devices is improved by applying a metal material to form the gate electrode whose volume increases when solidified and thereby applies a tensile stress to a channel.

The present application provides a semiconductor structure, which relates to the field of semiconductor technology and is used to solve the problem that the performance of semiconductor structure is difficult to improve. The semiconductor structure includes a substrate, including an isolation structure and an active region defined by the isolation structure; the gate trench disposed in the substrate; the gate electrode located in the gate trench and including a gate semiconductor layer; voids located in the gate trench, at least one of the voids is connected to the gate semiconductor layer. In the present application, by disposing the voids in the gate trench and enabling at least one of the voids to connect with the gate semiconductor layer, the small size of the semiconductor structure can be ensured, while the performance of the semiconductor structure can be improved.

A semiconductor device having a transistor structure is described. The transistor structure comprises a fin active region vertically protruding from a substrate and extending in a first horizontal direction; and a gate structure crossing the fin active region and extending in a second horizontal direction. The gate structure includes an upper gate structure disposed over the fin active region, the upper gate structure having a line shape extending in the second horizontal direction; and a lower gate structure disposed on both sides of the fin active region. The lower gate structure has a first horizontal width in the first horizontal direction. The upper gate structure has a second horizontal width in the first horizontal direction. The first horizontal width is less than the second horizontal width.

Some embodiments of the disclosure provide an apparatus comprising a memory cell array region, and a peripheral region including a silicon-on-insulator (SOI) complementary metal-oxide-silicon (CMOS) transistor. The SOI CMOS transistor pair includes a buried oxide (BOX) layer in a semiconductor substrate, and an SOI layer on the BOX layer. The SOI layer has a thickness such that a depletion layer when formed in the SOI layer fills the SOI layer between a gate and the BOX layer and between source/drain regions.

A semiconductor device is provided. The semiconductor device includes a substrate, first and second wells, first to third doped regions and a segmented gate. The first well having a first conductivity type and the second well having a second conductivity type are disposed in the substrate. The first doped region having the first conductivity type and the second doped region having the second conductivity type are disposed in the first well. The third doped region having the second conductivity type is disposed in the second well. The segmented gate is disposed on the first and the second wells. The segmented gate includes a first gate electrode segment of the second conductivity type, a second gate electrode segment of the first conductivity type and a third gate electrode segment of the first conductivity type. The first gate electrode segment is disposed between the second and third gate electrode segments.

A semiconductor structure includes a pad layer, a trench, a gate and two protecting parts. The trench passes through the pad layer along a direction. The gate is in T-shape, and is disposed on the pad layer, and extends into the trench. The gate includes a first part and a second part. The first part is disposed on the pad layer, and includes two side walls and a first metal layer. The second part is connected to the first part, and is located in the trench. The two protecting parts are respectively covered the two side walls, and the first metal layer is disposed between the two protecting parts. Thus, the semiconductor structure can prevent the element characteristics from being affected.

The present application discloses a thin film transistor and an array substrate. The thin film transistor includes a gate electrode, a source electrode, and a drain electrode, and at least one of the gate electrode, the source electrode, or the drain electrode is a composite film layer. The composite film layer includes a metal layer, a low reflection functional layer, and an alloy layer which are arranged in layers. The alloy layer covering a surface of the low reflection functional layer can enhance stability of the low reflection functional layer. Because adhesion between the alloy layer and dielectric layers such as silicon oxide, silicon nitride, and silicon oxynitride is stronger than that of the low reflection functional layer, the bulge phenomenon is not easy to occur under a high temperature environment.

Complementary Field-Effect Transistors (CFETs) are formed having different combinations of work function metal layers that produce different threshold voltages. A method includes forming first nanostructures over a first region of a substrate; forming second nanostructures over a second region of the substrate; forming third nanostructures over a third region of the substrate; depositing a first gate electrode layer on the first nanostructures; depositing a second gate electrode layer on the second nanostructures and on the first gate electrode layer on the first nanostructures; depositing a third gate electrode layer on the third nanostructures, on the second gate electrode layer on the second nanostructures, and on the second gate electrode layer on the first nanostructures; and depositing a fourth gate electrode layer on the third gate electrode layer, on the first nanostructures, on the second nanostructures, and on the third nanostructures.

An exemplary stacked device structure includes a semiconductor layer stack disposed over a substrate and a dual work function metal (DWFM) gate. The semiconductor layer stack includes a first semiconductor layer disposed over a second semiconductor layer. The DWFM gate includes a first gate dielectric layer, a second gate dielectric layer, a first type work function metal layer, and a second type work function metal layer. The first gate dielectric layer is disposed over the first semiconductor layer, and the second gate dielectric layer is disposed over the second semiconductor layer. The first type work function metal layer is disposed over the first gate dielectric layer, and the second type work function metal layer is disposed over the second gate dielectric layer. At least one of the first type work function metal layer or the second type work function metal layer has a gradient composition.