The present disclosure discloses a gate-all-around field effect transistor which not only can suppress the occurrence of punch through in the substrates and direct leakage of current from the source region/drain region into the part under the channels, but also can facilitate heat release of the substrate, and minimizes the occurrence of device defects due to misalignment between the trench inner spacers and the device by forming trench inner spacers (TISs) and thus preventing source region/drain region impurities from diffusing into the substrate, and a method for manufacturing the same.

A transistor and a method for fabricating the transistor are provided. The semiconductor structure transistor includes a base, a low-dimensional material layer, a plurality of spacers, a source, a drain, and a gate stack. The low-dimensional material layer is provided above the base. The plurality of spacers is provided on a surface of the low-dimensional material layer away from the base and spaced apart from each other. The source and the drain are provided on the surface of the low-dimensional material layer away from the base, respectively. The gate stack is provided on the surface of the low-dimensional material layer away from the base and between the source and the drain, in which the gate stack, the source and the drain are separated by the spacers, and in contact with the spacers, respectively. Therefore, the transistor has advantages of excellent comprehensive performance, high process compatibility, and good device uniformity.

A semiconductor structure includes a pad layer, a trench, a gate and two protecting parts. The trench passes through the pad layer along a direction. The gate is in T-shape, and is disposed on the pad layer, and extends into the trench. The gate includes a first part and a second part. The first part is disposed on the pad layer, and includes two side walls and a first metal layer. The second part is connected to the first part, and is located in the trench. The two protecting parts are respectively covered the two side walls, and the first metal layer is disposed between the two protecting parts. Thus, the semiconductor structure can prevent the element characteristics from being affected.

A device includes a plurality of nanosheets over a substrate, a source/drain feature adjacent to the plurality of nanosheets, and a gate structure disposed over the plurality of nanosheets and between adjacent nanosheets. Gate spacers are disposed over sidewalls of opposing sides of a top portion of the gate structure. Inner spacers interpose lateral ends of adjacent ones of the plurality of nanosheets in a first direction and interpose portions of the gate structure and the source/drain feature in a second direction. Each of the inner spacers includes a core layer and a liner layer disposed on a top and bottom surfaces of the core layer. There is an offset of a dimension of the plurality of nanosheets in a third direction at an interface between portions of the nanosheets underneath the gate spacers and portions of the nanosheets underneath the top portion of the gate structure.

A semiconductor structure is provided. The semiconductor structure includes channel members disposed above a substrate, a gate structure wrapping around the channel members, inner spacers adjacent to the gate structure, and a source/drain feature abutting the channel members. One of the inner spacers includes a middle dielectric portion and a shield dielectric portion that covers surfaces of the middle dielectric portion. The dielectric constant of the shield dielectric portion is greater than the dielectric constant of the middle dielectric portion.