An integrated circuit semiconductor device includes a plurality of fin-type active regions protruding from a substrate and spaced apart from each other, nano sheet stacking structures on the fin-type active regions, placeholders within the fin-type active regions, source and drain regions on the placeholders, a dielectric wall structure between a pair of the fin-type active regions and separating the pair of fin-type active regions, the nano sheet stacking structures thereon, the placeholders therein, and the source and drain regions thereon. The field regions are within trenches in the substrate, which separate the fin-type active regions. The field regions each include a multi-insulating layer. A plurality of gate structures are provided on the nano sheet stacking structures.

A semiconductor device includes a substrate, a lower channel stack on the substrate, an upper channel stack on the lower channel stack, a gate electrode extending around the lower channel stack and the upper channel stack, a gate cut region that is on the substrate and includes an insulating material, a semiconductor material layer between the upper channel stack and the gate cut region, and an insulating layer that is between the semiconductor material layer and the upper channel stack.

An integrated circuit device may include at least one first semiconductor pattern extending in a first horizontal direction, a first source/drain region connected to an end of the at least one first semiconductor pattern in the first horizontal direction, at least one second semiconductor pattern extending in the first horizontal direction and spaced apart from the at least one first semiconductor pattern in a second horizontal direction, a second source/drain region connected to an end of the at least one second semiconductor pattern in the first horizontal direction, and an insulating wall in an insulating wall opening that extends in the first horizontal direction, between the at least one first semiconductor pattern and the at least one second semiconductor pattern and between the first source/drain region and the second source/drain region.

A semiconductor device including a first fin pattern and a second fin pattern, a first source/drain pattern overlapping the first fin pattern, a second source/drain pattern overlapping the second fin pattern, a lower separation dielectric layer between the first and second fin patterns and between the first and second source/drain patterns, a cover dielectric layer on the first source/drain pattern and the second source/drain pattern, and an upper separation dielectric layer overlapping the lower separation dielectric layer may be provided. A lower portion of the upper separation dielectric layer may be between the first source/drain pattern and the second source/drain pattern. An upper portion of the upper separation dielectric layer may be at a level higher than a level of the cover dielectric layer.

A semiconductor device includes a substrate including a logic cell region and an alignment mark region, a first active pattern on the substrate and in the logic cell region, the first active pattern extending in a first horizontal direction, a second active pattern on the substrate and in the logic cell region, the second active pattern extending in the first horizontal direction and spaced apart from the first active pattern in a second horizontal direction that is different from the first horizontal direction, and a channel isolation layer on the substrate and in the logic cell region, the channel isolation layer extending in the first horizontal direction and isolating the first active pattern from the second active pattern in the second horizontal direction, where sidewalls of the channel isolation layer that are across the second horizontal direction contact the first active pattern and the second active pattern.