A semiconductor substrate of a semiconductor device has: a deep region provided at a boundary between an element region and a peripheral region; a RESURF region provided in the peripheral region and shallower than the deep region; and a local region protruding downward from the RESURF region. The local region is disposed away from the deep region and has a bottom surface located deeper than the deep region.

There is provided a semiconductor device which includes a plurality of transistor regions; a gate pad provided above a semiconductor substrate; a plurality of gate wiring portions each of which corresponds to each of the plurality of transistor regions; and a plurality of wiring resistance portions each of which is electrically connected to the gate pad and corresponds to each of the plurality of gate wiring portions. The plurality of gate wiring portions may include a gate metal layer provided above the semiconductor substrate and a gate runner provided below the gate metal layer. A built-in resistance portion may be electrically connected between the gate pad and the plurality of gate wiring portions.

Provided is a semiconductor device including a drift region of a first conductivity type which is provided in a semiconductor substrate, a plurality of trench portions which have a gate trench portion and a dummy trench portion and are arranged at a predetermined pitch in a trench array direction, and an outer circumferential well region of the second conductivity type which is provided on an outer circumference of the semiconductor substrate relative to the plurality of trench portions, in which the plurality of trench portions are provided to be spaced apart from the outer circumferential well region, and a difference between an end portion of the gate trench portion and an end portion of the dummy trench portion in a trench extension direction is less than or equal to twice the pitch.

A semiconductor device includes: a semiconductor body; an insulation layer on a surface of the semiconductor body, and having an opening that exposes the surface of the semiconductor body; and a surface electrode on a region overlapping at least the opening and connected with the semiconductor body at the opening. The semiconductor body includes: an n-type drift layer; a p-type dopant region that is formed on a surface layer portion of the drift layer and is in contact with the surface electrode; and columnar regions arranged in a region where the p-type dopant region is formed at a predetermined interval, having dopant concentration higher than dopant concentration of the p-type dopant region and deeper than the p-type dopant region, and the columnar regions that are disposed adjacently to a predetermined columnar region are formed at positions that are vertices of a regular hexagonal shape as viewed in a plan view.

Provided is a semiconductor device which includes a diode portion, the semiconductor device includes: a drift region of a first conductivity type which is provided in a semiconductor substrate; a plurality of trench portions which extend in a predetermined trench extending direction on a front surface side of the semiconductor substrate; and a front-surface electrode portion which is provided above a front surface of the semiconductor substrate, the diode portion includes a plug region of a second conductivity type which is provided in the semiconductor substrate and in contact with the front-surface electrode portion, and a first conductivity type mesa region of the first conductivity type which is in contact with the plug region in a mesa portion between the plurality of trench portions.

A power semiconductor device includes: first and second load terminals at respective front and back sides of a semiconductor body; in the semiconductor body and electrically connected with the first load terminal at the front side within an active region, a doped front side region of a second conductivity type; in the semiconductor body within an edge termination region, a VLD region of the second conductivity type coupled to the doped front side region and having a laterally varying dopant concentration that decreases in a direction from the active region towards a chip edge; at the front side, in the edge termination region, adjacent to the first load terminal and laterally overlapping with the VLD region, an insulation layer; and, above the insulation layer, in the edge termination region and laterally overlapping with the VLD region at least partially, a conductor coupled to a potential of the first load terminal.

A semiconductor device includes: a drift layer of a first conductivity-type provided in an active area and an edge termination area surrounding the active area; a base region of a second conductivity-type provided on a top surface side of the drift layer in the active area; a main region of the first conductivity-type provided on a top surface side of the base region; and an insulated gate electrode structure provided in contact with the main region and the base region, wherein an effective carrier concentration in the base region is relatively high in a middle part of the active area and is relatively low in a circumferential part of the active area, and a depth of a peak concentration in the base region is deeper than a bottom surface of the main region.

A semiconductor device includes a first electrode; a first semiconductor region of a first conductivity type on the first electrode and including a first region and a second region positioned around the first region; a second semiconductor region of a second conductivity type on the first region; a third semiconductor region of the first conductivity type on the second semiconductor region; a gate electrode facing the second semiconductor region via a gate insulating layer; a fourth semiconductor region of the second conductivity type on the second region and spaced apart from the second semiconductor region; a second electrode provided on the third semiconductor region via a first contact; a third electrode provided on the fourth semiconductor region via a second contact. The first and second contacts each include a titanium-containing layer, a titanium nitride-containing layer on the titanium-containing layer, and a tungsten-containing layer on the titanium nitride-containing layer.

A semiconductor device includes a plurality of trenches formed on a first main surface of a semiconductor substrate, and insulating films and electrodes formed in the plurality of trenches. The plurality of trenches include a first trench and a second trench deeper than the first trench and wider than the first trench. A bottom layer of a second conductivity type, in contact with a bottom of the second trench and not in contact with the first trench, is disposed under the second trench.

Provided is a method for manufacturing a semiconductor device, including forming a plurality of trenches at a front surface of a semiconductor substrate, forming an implantation mask in a first trench of the plurality of trenches, and implanting a dopant of a second conductivity type in a second trench, among the plurality of trenches, in which the implantation mask is not formed, to form a trench bottom portion in a bottom portion of the second trench, wherein in the implanting the dopant, the dopant of the second conductivity type is also implanted in a first mesa portion adjacent to the first trench and a second mesa portion adjacent to the second trench.