Patent classifications
H01L21/98
Component carrier comprising pillars on a coreless substrate
A component carrier includes a stack with an electrically conductive layer structure and an electrically insulating layer structure. The electrically conductive layer structure having a first plating structure and a pillar. The pillar has a seed layer portion on the first plating structure and a second plating structure on the seed layer portion. A method of manufacturing such a component carrier and an arrangement including such a component carrier are also disclosed.
Silicon package having electrical functionality by embedded passive components
A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.
Structure and formation method of chip package with fan-out feature
A package structure and a formation method of a package structure are provided. The method includes forming a redistribution structure over a carrier substrate and disposing a semiconductor die over the redistribution structure. The method also includes stacking an interposer substrate over the redistribution structure. The interposer substrate extends across edges of the semiconductor die. The method further includes disposing one or more device elements over the interposer substrate. In addition, the method includes forming a protective layer to surround the semiconductor die.
LED packaging with integrated optics and methods of manufacturing the same
Methods and structures are provided for wafer-level packaging of light-emitting diodes (LEDs). An array of LED die are mounted on a packaging substrate. The substrate may include an array of patterned metal contacts on a front side. The metal contacts may be in electrical communication with control logic formed in the substrate. The LEDs mounted on the packaging substrate may also be encapsulated individually or in groups and then singulated, or the LEDs mounted on the packaging substrate may be integrated with a micro-mirror array or an array of lenses.