An electromigration (EM) sign-off methodology that analyzes an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat sink elements located within a defined thermal coupling volume or range.

System and methods to generate a circuit design for an integrated circuit using only allowable pairs of connected logic stages. The allowable pairs of connected logic stages are those pairs of connected logic stages with a static noise margin (SNM) above an SNM threshold. Also presented is a 16-bit microprocessor made entirely from carbon nanotube field effect transistors (CNFET) having such allowable pair of connected logic stages.

A method for compensation network design in a power converter design system is provided that includes computing optimal values for compensation components in a compensation network based on a plurality of loop specifications comprising crossover frequency (Fco), phase margin (PM), Gain Margin (GM), and low frequency gain (LFG), and applying changes to a power converter design comprising the compensation network based on the optimal values.

Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

Disclosed is a method for evaluating computational fluid dynamic simulation results. The method includes: performing at least two baseline runs of a simulated area or volume containing a first vehicle body shape using a set of initial conditions, performing a change run using a second vehicle body using the set of initial conditions, creating a noise map based on differences between the second baseline run and the first baseline run, creating a change map based on differences between the change run and a selected baseline run, and comparing the change map to the noise map.

A non-transitory computer readable recording medium includes simulation data input into a computing device executing a simulation of a semiconductor device, wherein the simulation data includes part shape information describing shape and terminal information of the semiconductor device, logical model information describing operation and connection information of an element in the semiconductor device, and functional block information describing positional information of a functional block in the semiconductor device, and the computing device causes the part shape information, the logical model information, and the functional block information to correspond to each other to execute the simulation of the semiconductor device.

This application provides a quantum noise process analysis method, system, storage medium, and electronic device, which are applied in the field of quantum information processing technology. The method includes: preparing quantum initial states; respectively inputting the quantum initial states into a plurality of first circuits to obtain a plurality of first quantum output states; determining a first dynamical map eigenspectrum according to a functional correspondence between the plurality of first quantum output states and the quantum initial states; respectively inputting the quantum initial states into a plurality of second circuits to obtain a plurality of second quantum output states; determining a second dynamical map eigenspectrum according to a functional correspondence between the plurality of second quantum output states and the quantum initial states; and determining a dynamical map eigenspectrum of a quantum noise process according to the first dynamical map eigenspectrum and the second dynamical map eigenspectrum.

An electromigration (EM) sign-off methodology that utilizes a system for analyzing an integrated circuit design layout to identify heat sensitive structures, self-heating effects, heat generating structures, and heat dissipating structures. The EM sign-off methodology includes a memory and a processor configured for calculating adjustments of an evaluation temperature for a heat sensitive structure by calculating the effects of self-heating within the temperature sensitive structure as well as additional heating and/or cooling as a function of thermal coupling to surrounding heat generating structures and/or heat dissipating elements located within a defined thermal coupling volume or range of the heat sensitive structures.

In some implementations, a metrology optimization system may obtain three-dimensional (3D) model information associated with an object. The metrology optimization system may obtain optical sensor information associated with a metrology system that is to measure the object. The metrology optimization system may determine, based on the 3D model information and the optical sensor information, an initial configuration for the metrology system. The metrology optimization system may determine, based on the 3D model information, the optical sensor information, and the initial configuration, an optimal configuration for the metrology system. The metrology optimization system may provide the optimal configuration for the metrology system.

A method, system, and computer program product are disclosed for implementing enhanced noise impact on function (NIOF) analysis of an IC design having nets in multiple different variable voltage domains next to each other and modeling all multiple worst-case victim-aggressor voltage configurations in a single run leveraging noise abstracts characterized at a single voltage corner. The NIOF analysis enables accurately identifying incorrect victim switching or functional fails, effectively and efficiently providing design verification and the ability to sign-off an IC design with a single run, and enable modifying an integrated circuit design to fix NIOF failures, and fabricating an integrated circuit.