A three-layer vertical shunt resistor, a power semiconductor and a method for manufacturing a three-layer vertical shunt resistor are disclosed. The three-layer vertical shunt resistor includes a first resistor body including a resistive material, a second resistor body coupled to an upper portion of the first resistor body and formed of a resistive material having better electrical conductivity than the resistive material of the first resistor body, a first terminal coupled to a lower portion of the first resistor body and formed of a metal material having better electrical conductivity than the resistive material of the first resister body, and a second terminal coupled to a lower portion of the first resistor body and arranged to be spaced apart from the first terminal and formed of a metal material having better electrical conductivity than the resistive material of the first resistor body.

A method is provided for forming a thin film resistor (TFR) and a thin film MIM capacitor (TFMIMCAP) in an integrated circuit (IC) device. A method comprises: forming a thin film layer over an integrated circuit (IC) structure; annealing the thin film layer; and forming first and second thin film elements in the thin film layer. An integrated circuit device comprises: an integrated circuit (IC) structure; an annealed thin film layer above the IC structure; and first and second thin film elements in the thin film layer.

A method is provided for forming a thin film resistor (TFR) and a thin film MIM capacitor (TFMIMCAP) in an integrated circuit (IC) device. A method comprises: forming a thin film layer over an integrated circuit (IC) structure; annealing the thin film layer; forming a thin film sacrificial hardmask on the thin film layer; forming first and second thin film elements in the thin film layer; and removing the thin film sacrificial hardmask. An integrated circuit device comprises: an integrated circuit (IC) structure; an annealed thin film layer above the IC structure; and first and second thin film elements in the thin film layer, wherein the integrated circuit device does not comprise a thin film hardmask.

This nitride semiconductor device includes: a conductive substrate having a substrate upper surface; a high-resistance layer; a nitride semiconductor layer formed on the high-resistance layer; a first electrode (source electrode) formed on the nitride semiconductor layer; and a via. The high-resistance layer is formed on the substrate upper surface, and has a higher resistance value than does the conductive substrate. The via is electrically connected to the first electrode (source electrode), is provided so as to pass through the nitride semiconductor layer and the high-resistance layer, and contacts the substrate upper surface.