Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

A field-effect transistor includes a substrate, a channel on the substrate including a stem including silicon extending in a vertical direction from the substrate and a number of prongs including silicon extending in a horizontal direction from the stem and spaced apart from each other along the vertical direction, an interfacial layer surrounding the stem and the prongs of the channel, a dielectric layer on the interfacial layer and surrounding the stem and the prongs of the channel, and a metal gate on the dielectric layer and surrounding the stem and the prongs of the channel.

A semiconductor device includes a first inductor including a first coil wiring located on a first plane, a second coil wiring of which at least a part is located on the first plane, and a drive circuit that supplies a common signal to the first coil wiring and the second coil wiring. A first region surrounded by the first coil wiring and a second region surrounded by the second coil wiring overlap each other in a direction that is perpendicular to the first plane.

A power supply circuit includes: a feedback control circuit configured to control a switch output stage for generating an output voltage of a secondary circuit system from an input voltage of a primary circuit system while isolating between the primary circuit system and the secondary circuit system; and an overcurrent protection circuit configured to restrict a sense voltage corresponding to a primary current of the switch output stage to a predetermined overcurrent detection value or less. The overcurrent protection circuit stepwise increases the overcurrent detection value over a soft start period when a second power supply voltage is started or restarted.

An integrated electrical device that includes an energy storage component, the component having, above a support, a bottom electrode layer, an intermediate layer having a dielectric layer or an ionic conductor layer above the bottom electrode layer, and a top electrode layer above and on the intermediate layer, wherein the intermediate layer is in contact with the bottom electrode layer and with the top electrode layer in a central region, and the intermediate layer is are spaced apart from either the bottom electrode layer or the top electrode layer by a buffer layer in a peripheral region that surrounds the central region, the buffer layer including an insulating material and arranged on the bottom electrode layer or on the intermediate layer, the buffer layer having an opening that opens onto the bottom electrode layer or onto the intermediate layer so as to define the central region.

An electronic component, an electronic circuit, and a method for manufacturing an electronic component. An electronic component includes a substrate having first and second main surfaces facing each other and containing a silicon element; a capacitor element on the first main surface; and an inductor element on the first or second main surfaces in a direction orthogonal to the first main surface with respect to the capacitor element and electrically connected to the capacitor element. The capacitor element includes a first electrode portion extending in a direction intersecting the first main surface between the first and second main surfaces; a second electrode portion that extends in the direction intersecting the first main surface between the first and second main surfaces, and faces the first electrode portion in a direction parallel to the first main surface; and a dielectric portion between the first and second electrode portions.

An apparatus, system, and method for the manufacturing of an inductor having a high quality factor using deep trench isolation (DTI) is disclosed. The apparatus may include a substrate doped to form a well. The apparatus may also include an inductor coil above a surface of the substrate. The apparatus may further include a trench etched in the substrate, a dielectric in the trench, and a conductor within the dielectric in the trench. The conductor may be biased to create a depletion region below the inductor coil.