A Semiconductor device includes a semiconductor substrate, an insulating film, a first conductive film, a ferroelectric film, an insulating layer, a first plug and a second plug. The semiconductor substrate includes a source region and a drain region which are formed on a main surface thereof. The insulating film is formed on the semiconductor substrate such that the insulating film is located between the source region and the drain region in a plan view. The first conductive film is formed on the insulating film. The ferroelectric film is formed on the first conductive film. The insulating layer covers the first conductive film and the ferroelectric film. The first plug reaches the first conductive film. The second plug reaches the ferroelectric film. A material of the ferroelectric film includes hafnium and oxygen. In plan view, a size of the ferroelectric film is smaller than a size of the insulating film.

A semiconductor device is provided, which comprises: a die layer; a trench extending into the die layer, wherein the trench comprises a trench bottom and trench side walls; a first dopant implantation region arranged below the trench bottom; a second dopant implantation region arranged below the first dopant implantation region; a first dopant diffusion layer extending laterally of the first dopant implantation region; and a second dopant diffusion layer extending laterally of the second dopant implantation region; wherein an extension of the second dopant diffusion region in the lateral direction matches an extension of the first dopant diffusion layer in the lateral direction.

Disclosed is a method for producing a semiconductor device, the method including forming a plurality of semiconductor arrangements one above the other, wherein forming each of the plurality of semiconductor arrangements includes forming a semiconductor layer, forming a plurality of trenches in a first surface of the semiconductor layer, and implanting dopant atoms of at least one of a first type and a second type into at least one of a first sidewall and a second sidewall of each of the plurality of trenches. Forming of at least one of the plurality of semiconductor arrangements further includes forming a protective layer covering mesa regions between the plurality of trenches of the respective semiconductor layer, and covering a bottom, the first sidewall and the second sidewall of each of the plurality of trenches that are formed in the respective semiconductor layer.

A semiconductor device includes: a substrate; a main drift layer provided over the substrate; a current dispersion layer provided over the main drift layer; a sub-drift layer provided over the current dispersion layer; a second conductivity type blocking layer provided in contact with the sub-drift layer, and having a groove; a second conductivity type body layer provided over the sub-drift layer and the second conductivity type blocking layer; a high concentration first conductivity type impurity-containing layer provided over the second conductivity type body layer; a gate trench in a groove shape extending from the high concentration first conductivity type impurity-containing layer to at least the sub-drift layer; a gate insulating film; and a gate electrode as defined herein, and a bottom portion of the gate trench is located closer to the high concentration first conductivity type impurity-containing layer than a bottom surface of the second conductivity type blocking layer.

A p-type impurity concentration in a p-type trench underlayer is appropriately adjusted. A method for producing a field effect transistor includes: a body layer formation step of forming a p-type body layer by ion-implanting a p-type impurity; a trench formation step of forming a trench in an upper surface of a semiconductor substrate; a p-type trench underlayer formation step of forming the p-type trench underlayer below the trench by implanting a p-type impurity into a bottom surface of the trench while the upper surface of the semiconductor substrate is covered with an ion implantation mask; and a gate electrode formation step of forming a gate insulating film and a gate electrode in the trench. In the p-type trench underlayer formation step, the p-type impurity is implanted at a higher concentration than in the body layer formation step.

A method for preparing a super junction trench MOSFET, comprising: providing a substrate, and forming a first trench in the substrate; depositing an epitaxial portion of a first stage in the first trench while supplying a doped gas and an etching gas, and performing an epitaxial process after stopping supplying the doped gas and the etching gas, wherein impurities in the epitaxial portion of the first stage are diffused to an upper portion of the first trench and to form an epitaxial portion of a second stage with a gradient concentration by utilizing a high-temperature environment of the epitaxial process; forming a well region, a trench gate, and an active region in the substrate at a periphery of the first trench; forming an interlayer dielectric layer covering the column, the trench gate, and the active region; and electrically leading out the column, the trench gate, and the active region.