A new field-effect transistor (FET) based switch for use in/with high voltage precision instruments is provided. The switch can enable leakage compensation. A switch comprises a first FET in series with a second FET, and a buffer with an output terminal and an input terminal. The drain terminal of the first FET is connected to the source terminal of the second FET. The input terminal is coupled to the drain terminal of the second FET. At least one of: the first FET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the first FET; and, the second SFET has an isolation terminal and the output terminal of the buffer is coupled to the isolation terminal of the second FET.

A method of manufacturing a semiconductor device includes: forming a well region of a second conductivity-type on a top surface side of a semiconductor base-body of a first conductivity-type; forming a plurality of channel formation regions of the first conductivity-type on a top surface side of the well region; forming a plurality of drift regions on the top surface side of the well region alternately with the channel formation regions; forming a plurality of gate electrodes on top surface sides of the respective channel formation regions with a gate insulating film interposed; and forming a wiring layer arranged over the well region, wherein forming the well region including: forming a plurality of first ion implantation regions formed into slits and having different widths, and forming a second ion implantation region at a position overlapping with the wiring layer on an end part side of the first ion implantation regions having a relatively narrow width; and forming the well region by annealing.

An integrated circuit including a high voltage semiconductor device having a first doped region, a second doped region, and a drift region located between the first doped region and the second doped region. The circuit includes a plurality of stacked metal layers, a metal structure overlapping the drift region, and a field plate structure arranged between the metal structure and the drift region. The field plate structure includes an array of floating field plates, and a pair of field plates, having first and second field plates, wherein the pair of field plates overlaps the array of floating field plates. The first field plate and the second field plate are separated by a gap, and the gap is arranged diagonally over the drift region.

A lateral-conduction MOSFET device includes a semiconductor body and source regions of a first conductivity type extending into the body along a first direction at a distance from each other along a second (transverse) direction. Each source region has a first portion and a second portion along the first direction. Body contact regions, distinct from each other, one for each source region, of a second conductivity type extend into the body alongside and in contact with the respective first portion parallel to the second direction. The first portion of each source region and the respective body contact region together have a first width along the second direction. The second portion of each source region has a respective second width along the second direction. The first width is greater than the second width.

The present disclosure provides an LDMOS device and a preparation method thereof, including: providing a substrate including a first drift region of a first conductivity type and a body region of a second conductivity type; forming a first gate structure and a first blocking structure, where the first gate structure is formed above a portion of the body region and a portion of the first drift region, the body region and the first drift region respectively include first and second regions not covered by the first gate structure, and the first blocking structure is formed above the second region; performing an ion implantation process, where a part of ions are implanted into the first region of the body region to form a body region contact region, and a part of ions are implanted into the second region after passing through the first blocking structure to form a first doped region.

The present invention provides a level shifter, a semiconductor device, and preparation methods thereof. In the level shifter, a non-doped region and/or an inversion doped region are formed in at least one isolation doped region, so that an overall number of ions in the isolation doped region is reduced. This helps reduce difficulty of depleting the isolation doped region transversely and improve overall voltage withstanding performance of the level shifter. In this way, isolation performance of an isolation area can be ensured while a breakdown voltage of the level shifter is improved, and it is ensured that electrical leakage does not occur between a high-voltage side circuit and a drain.

A semiconductor transistor comprising: a drain region; a plurality of source regions; and a plurality of gate regions interleaved with the source regions.

An n-type source region and an n-type drain region ND1 are formed in a semiconductor substrate. A gate electrode is formed via a gate insulating film on a portion of the semiconductor substrate located between the source region and the drain region. A p-type impurity region is: formed in a portion of the semiconductor substrate located under the drain region, under the gate electrode, and under the source region. An impurity concentration of the impurity region is higher than an impurity concentration of the semiconductor substrate. The impurity region is spaced apart from an upper surface of the semiconductor substrate.

The present disclosure provides an LDMOS device and a preparation method thereof, including: providing a substrate including a first drift region of a first conductivity type and a body region of a second conductivity type; forming a first gate structure and a first blocking structure, where the first gate structure is formed above a portion of the body region and a portion of the first drift region, the body region and the first drift region respectively include first and second regions not covered by the first gate structure, and the first blocking structure is formed above the second region; performing an ion implantation process, where a part of ions are implanted into the first region of the body region to form a body region contact region, and a part of ions are implanted into the second region after passing through the first blocking structure to form a first doped region.

A semiconductor device includes a high voltage device. The high voltage device includes a central region with a first inner region. A termination area laterally surrounds the central portion and includes a first extension region. The first extension region is formed between the first inner region and a first outer region. A lightly doped base portion and the extension region form a pn junction. The central region further includes a second inner region. The second inner region and the first inner region are laterally separated and connected to different inner contact structures. Alternatively or in addition, the high voltage device further includes a second outer region, with the first outer region and the second outer region being laterally separated and connected to different outer contact structures.