A method of manufacturing a semiconductor device includes: forming a well region of a second conductivity-type on a top surface side of a semiconductor base-body of a first conductivity-type; forming a plurality of channel formation regions of the first conductivity-type on a top surface side of the well region; forming a plurality of drift regions on the top surface side of the well region alternately with the channel formation regions; forming a plurality of gate electrodes on top surface sides of the respective channel formation regions with a gate insulating film interposed; and forming a wiring layer arranged over the well region, wherein forming the well region including: forming a plurality of first ion implantation regions formed into slits and having different widths, and forming a second ion implantation region at a position overlapping with the wiring layer on an end part side of the first ion implantation regions having a relatively narrow width; and forming the well region by annealing.

This disclosure provides semiconductor device including a first transistor with a first gate terminal, a first source terminal, and the first drain terminal, the first transistor being a depletion mode transistor and including a plurality of two-dimensional carrier channels of a conductivity type being one of a n-type or a p-type conductivity. The semiconductor device also includes a second transistor with a second gate terminal, a second source terminal, and a second drain terminal, the second transistor being an enhancement mode transistor, a gate-source interconnect forming an electrical connection between the first gate terminal and the second source terminal, and a drain-source interconnect forming an electrical connection between the first source terminal and the second drain terminal. The first transistor and the second transistor are fabricated on the same wafer or substrate.

The present description concerns a method comprising providing a structure comprising a semiconductor substrate, conductive elements above the semiconductor substrate, a first intermetallic dielectric layer between the conductive elements, cavities in the first intermetallic dielectric layer between two adjacent conductive elements, and a second intermetallic dielectric layer above the first intermetallic dielectric layer and the cavities, the cavities being coupled together so as to form a continuous extended cavity between the two adjacent conductive elements, forming first, respectively second, ports running through the second intermetallic dielectric layer, extending to the cavities, respectively to the conductive elements, filling the first and second ports with a conductive material, the filling of the first ports filling the cavities, forming conductive regions coupled together, and thus a conductive track, and forming first conductive vias coupled to the conductive track, and filling the second ports forming second conductive vias coupled to the conductive elements.

Provided is a semiconductor device including a power distribution network layer on a lower surface of a substrate, a gate electrode on the substrate, a first source/drain pattern and a second source/drain pattern on the substrate, the first and second source/drain patterns each including a first pattern and a second pattern spaced apart from each other with the gate electrode therebetween, a through via structure penetrating the substrate and extending along a direction perpendicular to an upper surface of the substrate, the through via structure connecting the power distribution network layer and the first pattern of the first source/drain pattern, and a rear surface power via extending from below the second pattern of the first source/drain pattern to below the second pattern of the second source/drain pattern.

A semiconductor device includes: a semiconductor layer that includes a semiconductor substrate on a back face side and is divided into a first region, a second region, and a third region that do not overlap each other and are not dispersedly disposed in a plan view of the semiconductor device; a first vertical metal-oxide-semiconductor (MOS) transistor provided in the first region of the semiconductor layer; a second vertical MOS transistor provided in the second region of the semiconductor layer; and a drain pad connected to the semiconductor substrate, at a position within the third region in the plan view of the semiconductor device. In the plan view of the semiconductor device, the third region is interposed between the first region and the second region. In the plan view of the semiconductor device, an area of the first region is larger than an area of the second region.

The invention relates to a multilevel converter system comprising a multiplicity of energy storage modules and transistors, wherein each energy storage module can be connected in parallel with the respective adjacent energy storage module, can be connected in series therewith and/or can be bridged and has at least one energy storage cell, wherein at least two adjacent NPN transistors share an N-type zone and/or wherein at least two adjacent PNP transistors share a P-type zone.

Provided is a semiconductor device including a lower source/drain pattern, a lower channel structure connected to the lower source/drain pattern, a lower gate electrode overlapping the lower channel structure and extending in a first direction, a lower active contact on the lower source/drain pattern, an upper channel structure overlapping the lower channel structure, an upper source/drain pattern connected to the upper channel structure, an upper gate electrode overlapping the upper channel structure and extending in the first direction, an interlayer structure between the lower channel structure and the upper channel structure, and a through active contact extending through the interlayer structure, and electrically connected to the upper source/drain pattern and the lower active contact.

A low-noise amplifier structure utilizing horizontally stacked field-effect transistors (FETs) is described. The stacked FET structure includes two FETs stacked horizontally and connected in series (e.g., with a shared source/drain region). The stacked FET structure described a pitch between gates that is increased above a minimum pitch defined for a transistor region of the device. Increasing the pitch reduces a metallurgical channel length of a second FET in the stacked structure below what the metallurgical channel length would be at the minimum pitch. Reducing the metallurgical channel length improves the signal-to-noise ratio of the low-noise amplifier structure.