A nitride-based semiconductor circuit including a substrate structure, a nitride-based heterostructure, connectors, and connecting vias is provided. The substrate structure includes a first type semiconductor substrate, and a second type semiconductor substrate. The second type semiconductor substrate is embedded in a region of the first type semiconductor substrate. The first type semiconductor substrate has first dopants, and the second type semiconductor substrate has second dopants to form a pn junction between the first type semiconductor substrate and the second type semiconductor substrate. The nitride-based heterostructure is disposed on the substrate structure. The connectors are disposed on the nitride-based heterostructure. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first region of the first type semiconductor substrate to one of the connectors. The second interconnection electrically connects the second type semiconductor substrate to another one of the connectors.

The disclosure provides a method for fabricating a low resistance contact on a semiconductor substrate comprising a metal oxide semiconductor (MOS) device. The method comprises fabricating a via to a source or drain region of the MOS device, providing an insulating layer along a sidewall of the via while maintaining or reestablishing the exposed source or drain region, using ion implantation to implant a metallic element into the exposed source or drain region of the semiconductor substrate through the via to form an implanted layer, annealing the implanted layer to form a silicide layer comprising silicon and the metallic element on the source or drain region of the MOS device, and depositing a low resistance metal in the via to form the low resistance contact on the semiconductor substrate comprising the MOS device. The disclosure also provides a device comprising a low resistance contact fabricated by said method.

The present application relates to a semiconductor die, comprising a silicon carbide (SiC) semiconductor body comprising a first doping type region; a metallization on a first side of the SiC semiconductor body; an inorganic passivation layer system; a lateral edge of the inorganic passivation layer system arranged on the SiC semiconductor body, wherein the lateral edge of the inorganic passivation layer system is laterally offset inwards from a lateral edge of the SiC semiconductor body, the SiC semiconductor body being uncovered by the inorganic passivation layer system in an edge area, wherein a second doping type well is formed at the first side of the SiC semiconductor body in the first doping type region, the second doping type well extending from below the inorganic passivation layer system into the edge area.

An object is to provide a semiconductor device that enhances the reliability under high temperature and high humidity. The semiconductor device includes a semiconductor substrate, a first electrode, an insulating interlayer film, and at least one second electrode. The semiconductor substrate includes an active region through which a main current flows, and a termination region formed around the active region. The first electrode is formed in the active region. The insulating interlayer film is formed in the termination region on a front surface side of the semiconductor substrate. The at least one second electrode is formed in the termination region to annularly surround the active region. A part of the at least one second electrode is buried in the insulating interlayer film. A lower surface of the at least one second electrode is located below an upper surface of the insulating interlayer film.

A nitride-based semiconductor circuit including a substrate structure, a nitride-based heterostructure, connectors, and connecting vias is provided. The substrate structure includes a first type semiconductor substrate, and a second type semiconductor substrate. The second type semiconductor substrate is embedded in a region of the first type semiconductor substrate. The first type semiconductor substrate has first dopants, and the second type semiconductor substrate has second dopants to form a pn junction between the first type semiconductor substrate and the second type semiconductor substrate. The nitride-based heterostructure is disposed on the substrate structure. The connectors are disposed on the nitride-based heterostructure. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first region of the first type semiconductor substrate to one of the connectors. The second interconnection electrically connects the second type semiconductor substrate to another one of the connectors.

Integrated bilateral switch power device based on gallium nitride, including a die integrating a first and a second switch FET transistor, and a substrate-biasing network configured to electrically couple the substrate node selectively to the source region of the first and the second switch FET transistors which is at a lower potential. The substrate-biasing network has a first and second diode coupled in anti-series and formed by field effect, diode-connected transistors having the same structure as the first and the second switch FET transistors in the same conduction, contact and gate layers.