A transient voltage suppression (TVS) device, apparatus, structure and associated methods thereof. The TVS device includes a substrate, a first base layer, and a second base layer, the substrate coupled to the first base layer, and coupled to the second base layer, and one or more emitter layers formed in the first base layer.

A semiconductor device includes a first row of doped wells including first conductivity type wells arranged alternatingly with second conductivity type wells in a semiconductor body, a first electrically conductive contact formed on the semiconductor body electrically connected with one of the first conductivity type wells, a second electrically conductive contact formed on the semiconductor body electrically connected with one of the second conductivity type wells, and a trigger region that including a trigger element that is configured to generate a trigger current that induces direct current flow between the first and second conductivity type wells, wherein the trigger region comprises one or more current spreading interfaces that are configured to reduce a current density of the trigger current as it transitions between at least one of the first and second electrically conductive contacts and the semiconductor body.

A semiconductor device includes a first row of doped wells including first conductivity type wells arranged alternatingly with second conductivity type wells in a semiconductor body, a first electrically conductive contact formed on the semiconductor body electrically connected with one of the first conductivity type wells, a second electrically conductive contact formed on the semiconductor body electrically connected with one of the second conductivity type wells, and a trigger region that including a trigger element that is configured to generate a trigger current that induces direct current flow between the first and second conductivity type wells, wherein the trigger region comprises one or more current spreading interfaces that are configured to reduce a current density of the trigger current as it transitions between at least one of the first and second electrically conductive contacts and the semiconductor body.

A method of forming a semiconductor device includes forming a row of n-type wells and p-type wells in an upper surface of a semiconductor body, the p-type wells arranged alternatingly with the n-type wells, forming trigger regions in between the n-type wells and the p-type wells, the trigger regions including a low-doped section of the semiconductor body that is configured to induce current flow between the p-type wells and the n-type wells via avalanche breakdown, wherein the p-type wells and the n-type wells are formed by implanting dopant atoms into the upper surface of the semiconductor body, and wherein the low-doped section of the semiconductor body is formed by a hardmask that prevents the dopant atoms from penetrating the upper surface of the semiconductor body during the implanting of the dopant atoms.

A method of forming a semiconductor device includes forming a row of n-type wells and p-type wells in an upper surface of a semiconductor body, the p-type wells arranged alternatingly with the n-type wells, forming trigger regions in between the n-type wells and the p-type wells, the trigger regions including a low-doped section of the semiconductor body that is configured to induce current flow between the p-type wells and the n-type wells via avalanche breakdown, wherein the p-type wells and the n-type wells are formed by implanting dopant atoms into the upper surface of the semiconductor body, and wherein the low-doped section of the semiconductor body is formed by a hardmask that prevents the dopant atoms from penetrating the upper surface of the semiconductor body during the implanting of the dopant atoms.