Patent classifications
B81B7/0025
HIGH PERFORMANCE SEALED-GAP CAPACITIVE MICROPHONE
Some preferred embodiments include a microphone system for receiving sound waves, the microphone including a back plate, a radiation plate, first and second electrodes, first and second insulator layers, a power source and a microphone controller. The radiation plate is clamped to the back plate so that there is a hermetically sealed circular gap between the radiation plate and the back plate. The first electrode is fixedly attached to a side of the back plate proximate to the gap. The second electrode is fixedly attached to a side of the radiation plate. The insulator layers are attached to the back plate and/or the radiation plate, on respective gap sides thereof, so that the insulator layers are between the electrodes. The microphone controller is configured to use the power source to drive the microphone at a selected operating point comprising normalized static mechanical force, bias voltage, and relative bias voltage level. A radius and height of the gap, and a thickness of the radiation plate, are determined using the selected operating point so that a sensitivity of the microphone at the selected operating point is an optimum sensitivity for the selected operating point.
METHOD FOR PRODUCING A MICROELECTROMECHANICAL COMPONENT AND WAFER SYSTEM
A method for producing a microelectromechanical component as well as a wafer system includes steps of: providing a first wafer having a plurality of microelectromechanical base elements; forming a respective container structure on the microelectromechanical base elements at the wafer level; and disposing an oil or a gel within the container structures.
SENSOR PACKAGE
A sensor device may include a base layer, and an ASIC element disposed on the base layer. The ASIC element may include a plurality of electrical contact points. The sensor device may include a MEMS element. The MEMS element may include a plurality of through-silicon vias. The sensor device may include a plurality of conductive contact elements. Each conductive contact element may be disposed between, and electrically coupling, a respective through-silicon via and a respective electrical contact point. The sensor device may include a protective layer disposed between the ASIC element and the MEMS element. The protective layer may be composed of material(s) having a physical property defined to permit the protective layer to mitigate stress forces directed from the ASIC element to the MEMS element, to prevent corrosion, and/or to prevent leakage current between electrical connections due to pollution and/or humidity.
Microphone package for fully encapsulated ASIC and wires
A microphone device includes a housing including a substrate having a first surface and a cover disposed over the substrate, the housing including a sound port between the interior of the housing and the exterior of the housing. The device also includes a microelectromechanical systems (MEMS) transducer mounted on the substrate and an integrated circuit (IC) mounted on the substrate. The MEMS transducer of the device is electrically connected to the IC, and the IC of the device is electrically connected to a conductor on the substrate. An encapsulating material covers the IC. And an encapsulating material confinement structure is disposed between the MEMS transducer and the IC, wherein the encapsulating material confinement structure at least partially confines the encapsulating material around the IC.
STRESSED DECOUPLED MICRO-ELECTRO-MECHANICAL SYSTEM SENSOR
A semiconductor device may include a stress decoupling structure to at least partially decouple a first region of the semiconductor device and a second region of the semiconductor device. The stress decoupling structure may include a set of trenches that are substantially perpendicular to a main surface of the semiconductor device. The first region may include a micro-electro-mechanical (MEMS) structure. The semiconductor device may include a sealing element to at least partially seal openings of the stress decoupling structure.
Wearable device with combined sensing capabilities
The present invention discloses a wearable device with combined sensing capabilities, which includes a wearable assembly and at least one multi-function sensor module. The wearable assembly is suitable to be worn on apart of a user's body. The wearable assembly includes at least one light-transmissible window. The multi-function sensor module is located inside the wearable assembly, for performing an image sensing function and an infrared temperature sensing function. The multi-function sensor module includes an image sensor module for sensing a physical or a biological feature of an object through the light-transmissible window by way of image sensing; and an infrared temperature sensor module for sensing temperature through the light-transmissible window by way of infrared temperature sensing.
CMOS Based Devices for Harsh Media
A semiconductor device comprises a first doped semiconductor layer, a second doped semiconductor layer, an oxide layer covering the first doped semiconductor layer and the second doped semiconductor layer, and an interconnect. The first doped semiconductor layer is electrically connected with the second doped semiconductor layer by means of the interconnect which crosses over a sidewall of the second doped semiconductor layer. The interconnect comprises a metal filled slit in the oxide layer. At least one electronic component is formed in the first and/or second semiconductor layer. The semiconductor device moreover comprises a passivation layer which covers the first and second doped semiconductor layers and the oxide layer.
SEMICONDUCTOR DEVICE FOR USE IN HARSH MEDIA
A semiconductor device comprising a first and second doped semiconductor layer wherein the first layer is a monosilicon layer and the second layer is a polysilicon layer, an oxide layer covering the first and second layer, and an interconnect which electrically connects the first and second layer comprises a metal alloy which has a first part in contact with the first layer and a second part in contact with the second layer, wherein a part of the metal alloy between the first and the second part crosses over a sidewall of the second layer; at least one electronic component is formed in the first and/or second layer; the semiconductor device moreover comprises a stoichiometric passivation layer which covers the first and second layer and the oxide layer.
Wafer-level package with enhanced performance
The present disclosure relates to a wafer-level package that includes a first thinned die, a multilayer redistribution structure, a first mold compound, and a second mold compound. The first thinned die includes a first device layer formed from glass materials. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.
Method for producing a microelectromechanical sensor and microelectromechanical sensor
A method for producing a microelectromechanical sensor. The microelectromechanical sensor is produced by connecting a cap wafer to a sensor wafer. The cap wafer has a bonding structure for connecting the cap wafer to the sensor wafer. The sensor wafer has a sensor core having a movable structure. The cap wafer has a stop structure for limiting an excursion of the movable structure. The method includes a first step and a second step following the first step, the stop surface of the stop structure being situated at the level of the original surface of the unprocessed cap wafer.