Patent classifications
B81B7/0035
MICRO-ELECTROMECHANICAL SYSTEMS (MEMS) DEVICE WITH OUTGAS LAYER
The present disclosure relates to an integrated chip including a semiconductor device substrate and a plurality of semiconductor devices arranged along the semiconductor device substrate. A micro-electromechanical system (MEMS) layer overlies the semiconductor device substrate. The MEMS layer includes a first moveable mass and a second moveable mass. A capping layer overlies the MEMS layer. The capping layer has a first lower surface directly over the first moveable mass and a second lower surface directly over the second moveable mass. An outgas layer is on the first lower surface and directly between the first pair of sidewalls. A lower surface of the outgas layer delimits a first cavity in which the first moveable mass is arranged. The second lower surface of the capping layer delimits a second cavity in which the second moveable mass is arranged.
BARRIER STRUCTURE WITHIN A MICROELECTRONIC ENCLOSURE
An example method includes applying a dielectric material on at least a first portion of a first substrate; depositing a seed metal on the dielectric material and on at least a second portion of the first substrate; depositing a plating photoresist on at least a portion of the seed metal; electroplating a metal line on the seed metal within boundaries formed by the plating photoresist; stripping at least a portion of the plating photoresist, and etching at least a portion of the seed metal; and positioning a second substrate relative to a barrier structure formed in part by the metal line to form a cavity.
Method for manufacturing semiconductor structure
A method for manufacturing a semiconductor structure is provided. The method includes the operations as follows. A first substrate having a top surface is received. A semiconductor layer is formed over the first substrate. A cavity is formed at the top surface of the semiconductor layer. A second substrate is bonded over the first substrate to cover the semiconductor layer. The second substrate has a through hole connected to the cavity of the semiconductor layer. A eutectic sealing structure is formed on the second substrate to cover the through hole. The eutectic sealing structure includes a first metal layer and a second metal layer eutectically bonded on the first metal layer.