A wafer-level integrated thermal detector comprises a first wafer and a second wafer (W1, W2) bonded together. The first wafer (W1) includes a dielectric or semiconducting substrate (100), a dielectric sacrificial layer (102) deposited on the substrate, a support layer (104) deposited on the sacrificial layer or the substrate, a suspended active element (108) provided within an opening (106) in the support layer, a first vacuum-sealed cavity (110) and a second vacuum-sealed cavity (106) on opposite sides of the suspended active element. The first vacuum-sealed cavity (110) extends into the sacrificial layer (102) at the location of the suspended active element (108). The second vacuum-sealed cavity (106) comprises the opening of the support layer (104) closed by the bonded second wafer. The thermal detector further comprises front optics (120) for entrance of radiation from outside into one of the first and second vacuum-sealed cavities, aback reflector (112) arranged to reflect radiation back into the other one of the first and second vacuum-sealed cavities, and electrical connections (114) for connecting the suspended active element to a readout circuit (118).

A die-wrapped packaged device includes at least one flexible substrate having a top side and a bottom side that has lead terminals, where the top side has outer positioned die bonding features coupled by traces to through-vias that couple through a thickness of the flexible substrate to the lead terminals. At least one die includes a substrate having a back side and a topside semiconductor surface including circuitry thereon having nodes coupled to bond pads. One of the sides of the die is mounted on the top side of the flexible circuit, and the flexible substrate has a sufficient length relative to the die so that the flexible substrate wraps to extend over at least two sidewalls of the die onto the top side of the flexible substrate so that the die bonding features contact the bond pads.

A MEMS sensor includes a through hole to allow communication with an external environment, such as to send or receive acoustic signals or to be exposed to the ambient environment. In addition to the information that is being measured, light energy may also enter the environment of the sensor via the through hole, causing short-term or long-term effects on measurements or system components. A light mitigating structure is formed on or attached to a lid of the MEMS die to absorb or selectively reflect the received light in a manner that limits effects on the measurements or interest and system components.

A hermetically sealed package includes: at least one cover substrate and a substrate arranged so as to adjoin the at least one cover substrate, which together define at least part of the package, the at least one cover substrate being in a thermally prestressed state and bonded to the substrate adjoining the at least one cover substrate in a hermetically sealing manner by at least one laser bonding line, the at least one cover substrate being made of a material which has a different characteristic value of a coefficient of thermal expansion than the adjoining substrate and a thermal prestress is established in the package; and at least one functional area enclosed in the package.

A MEMS chip package is provided with a removable cover to allow non-destructive testing. The MEMS package has a container (with walls and a bottom) and a cover. The cover has a glass pane, and is secured to the MEMS package with an elastomeric gasket mounted between the walls of the MEMS package and the cover. A number of attachment mechanisms secure the cover to the MEMS package.

A wearable device includes a case and a far infrared temperature sensing device. The case has a first opening. The far infrared temperature sensing device is disposed inside the case of the wearable device. The far infrared temperature sensing device includes an assembly structure, a sensor chip, a filter structure, and a metal shielding structure. The assembly structure has an accommodating space and a top opening. The sensor chip is disposed in the accommodating space of the assembly structure. The filter structure is disposed above the sensor chip. The metal shielding structure is disposed above the sensor chip, and has a second opening to expose the filter structure. The first and second openings are communicated to cooperatively define a through hole.

A wearable device includes a case and a far infrared temperature sensing device. The case has a first opening. The far infrared temperature sensing device is disposed inside the case of the wearable device. The far infrared temperature sensing device includes an assembly structure, a sensor chip, a filter structure, and a metal shielding structure. The assembly structure has an accommodating space and a top opening. The sensor chip is disposed in the accommodating space of the assembly structure. The filter structure is disposed above the sensor chip. The metal shielding structure is disposed above the sensor chip, and has a second opening to expose the filter structure. The first and second openings are communicated to cooperatively define a through hole.

A complementary metal oxide semiconductor (CMOS) device embedded with microelectromechanical system (MEMS) components in a MEMS region. The MEMS components, for example, are infrared (IR) thermosensors. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the device using wafer-level vacuum packaging techniques.

A transmitting device, containing an emitting device (1) and a scanning mirror (2), which is deflectable about its center (MP) and is arranged in a housing (3) with a transparent cover element (4). The cover element (4) is formed, at least in a coupling-out region (4.2), by a section of a monocentric hemispherical shell (HK) with a center of curvature (K) and is arranged to cover the scanning mirror (2) in such a way that the center of curvature (K) of the hemispherical shell (HK) and the center (MP) of the scanning mirror (2) coincide.

Wafer level encapsulated packages includes a wafer, a glass substrate hermetically sealed to the wafer, and an electronic component. The glass substrate includes a glass cladding layer fused to a glass core layer and a cavity formed in the glass substrate. The electronic component is encapsulated within the cavity. In various embodiments, the floor of the cavity is planar and substantially parallel to a plane defined by a top surface of the glass cladding layer. The glass cladding layer has a higher etch rate in an etchant than the glass core layer. In various embodiments, the wafer level encapsulated package is substantially optically transparent. Methods for forming the wafer level encapsulated package and electronic devices formed from the wafer level encapsulated package are also described.