An inertial sensor according to the present disclosure includes a sensor element having a multilayer structure in which a first substrate, a second substrate, and a sensor substrate are stacked one on top of another. The first substrate includes a substrate body, a first interconnect, an electrode layer, and a silicon member. The first interconnect is provided inside the substrate body. The electrode layer is provided for the substrate body and electrically connected to the first interconnect. The silicon member is provided at an end of the substrate body. The silicon member has, in a cross-sectional view, a curved portion and a linear portion connected to the curved portion. The electrode layer is provided to cover the curved portion and the linear portion.

A semiconductor device may include a first substrate, a first electrical component, a lid, a second substrate, and a second electrical component. The first substrate may include an upper surface, a lower surface, and an upper cavity in the upper surface. The first electrical component may reside in the upper cavity of the first substrate. The lid may cover the upper cavity and may include a port that permits fluid to flow between an environment external to the semiconductor device and the upper cavity. The second substrate may include the second electrical component mounted to an upper surface of the second substrate. The lower surface of the first substrate and the upper surface of the second substrate may fluidically seal the second electrical component from the upper cavity.

A die attachment to a support is disclosed. In an embodiment, a semiconductor package includes a support and a die attached to the support by an adhesive on a backside of the die, wherein the die includes a capacitive pressure sensor integrated on a CMOS read-out circuit, and wherein the adhesive covers only a part of the backside of the die.

The present disclosure relates to semiconductor structures and, more particularly, to seal ring structures with channels and methods of manufacture. The structure includes: a first wafer having a channel formed within a passivation layer; a second wafer having a protuberance which is insertable into the channel and which is bonded to the first wafer with eutectic bonding materials; and a plurality of stoppers or tabs extending within the channel and which provides a gap that has a dimension smaller than a gap formed in other portions of the channel.

An integrated device package is disclosed. The integrated device package can include a packaging structure defining a cavity. An integrated device die can be disposed at least partially within the cavity. A gel can be disposed within the cavity surrounding the integrated device. A portion of the gel can be disposed between a lower surface of the integrated device die and an upper surface of the packaging structure within the cavity.

A method of manufacturing an electronic device includes providing a component carrier having a laminate of at least one electrically conductive layer structure and at least one electrically insulating layer structure, providing a mounting base for mounting an electronic component on and/or in the component carrier, and integrally forming a wall structure with the component carrier prior to mounting an electronic component on the mounting base, the integrally formed wall structure at least partially surrounding the mounting base for mounting the electronic component on the mounting base and protected by the wall structure.

A method of manufacturing an electronic device in which an electronic component coupled to a lead is covered with a mold cover, includes: a coupling step of coupling the electronic component to the lead, a bending step of bending the lead to adjust a posture of the electronic component, and a molding step of molding the electronic component with a resin material to form the mold cover, and the bending step includes a lead bending step of bending the lead by pressing a pressing member against the lead without pressing the pressing member against the electronic component.

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

Representative implementations of techniques and devices provide seals for sealing the joints of bonded microelectronic devices as well as bonded and sealed microelectronic assemblies. Seals are disposed at joined surfaces of stacked dies and wafers to seal the joined surfaces. The seals may be disposed at an exterior periphery of the bonded microelectronic devices or disposed within the periphery using the various techniques.

Apparatus(es) and method(s) relate generally to via arrays on a substrate. In one such apparatus, the substrate has a conductive layer. First plated conductors are in a first region extending from a surface of the conductive layer. Second plated conductors are in a second region extending from the surface of the conductive layer. The first plated conductors and the second plated conductors are external to the first substrate. The first region is disposed at least partially within the second region. The first plated conductors are of a first height. The second plated conductors are of a second height greater than the first height. A second substrate is coupled to first ends of the first plated conductors. The second substrate has at least one electronic component coupled thereto. A die is coupled to second ends of the second plated conductors. The die is located over the at least one electronic component.