B81C1/00523

METHOD AND DEVICE FOR A CARRIER PROXIMITY MASK

A carrier proximity mask and methods of assembling and using the carrier proximity mask may include providing a first carrier body, second carrier body, and set of one or more clamps. The first carrier body may have one or more openings formed as proximity masks to form structures on a first side of a substrate. The first and second carrier bodies may have one or more contact areas to align with one or more contact areas on a first and second sides of the substrate. The set of one or more clamps may clamp the substrate between the first carrier body and the second carrier body at contact areas to suspend work areas of the substrate between the first and second carrier bodies. The openings to define edges to convolve beams to form structures on the substrate.

Methods for Producing Thin-Film Layers and Microsystems Having Thin-Film Layers
20210017019 · 2021-01-21 ·

A method for producing a thin-film layer includes providing a layer stack on a carrier substrate, wherein the layer stack includes a carrier layer and a sacrificial layer, and wherein the sacrificial layer includes areas in which the carrier layer is exposed. The method includes providing the thin-film layer on the layer stack, such that the thin-film layer bears on the sacrificial layer and, in the areas of the sacrificial layer in which the carrier layer is exposed, against the carrier layer. The method includes at least partly removing the sacrificial layer from the thin-film layer in order to eliminate a contact between the thin-film layer and the sacrificial layer in some areas. The method also includes detaching the thin-film layer from the carrier layer.

METHODS FOR TUNING PLASMA POTENTIAL USING VARIABLE MODE PLASMA CHAMBER
20210020404 · 2021-01-21 ·

Plasma processing apparatus and associated methods are provided. In one example, a method can include admitting a process gas into a plasma chamber. The method can include exciting with RF energy an inductive coupling element to initiate ignition of a plasma induced in the process gas. The method can include adjusting an RF voltage of an electrostatic shield located between the inductive coupling element and the plasma chamber. The electrostatic shield can have a stray capacitance to a ground reference. The method can include conducting an ion-assisted etching process on the workpiece based at least in part on the RF voltage of the electrostatic shield.

Methods for producing thin-film layers and microsystems having thin-film layers

A method for producing a thin-film layer includes providing a layer stack on a carrier substrate, wherein the layer stack includes a carrier layer and a sacrificial layer, and wherein the sacrificial layer includes areas in which the carrier layer is exposed. The method includes providing the thin-film layer on the layer stack, such that the thin-film layer bears on the sacrificial layer and, in the areas of the sacrificial layer in which the carrier layer is exposed, against the carrier layer. The method includes at least partly removing the sacrificial layer from the thin-film layer in order to eliminate a contact between the thin-film layer and the sacrificial layer in some areas. The method also includes detaching the thin-film layer from the carrier layer.

Method of manufacturing MEMS switches with reduced switching voltage

An approach includes a method of fabricating a switch. The approach includes forming a first cantilevered electrode over a first electrode, forming a second cantilevered electrode over a second electrode and operable to directly contact the first cantilevered electrode upon an application of a voltage to at least one of the first electrode and a second electrode, and the first cantilevered electrode includes an arm with an extending protrusion which extends upward from an upper surface of the arm.

Method for manufacturing low contact resistance semiconductor structure

A method of manufacturing a semiconductor device includes providing a semiconductor structure having a bottom substrate, a sacrificial layer on the bottom substrate, and a top substrate on the sacrificial layer. The sacrificial layer has a first opening exposing a first portion of the bottom substrate and a second opening exposing a second portion of the bottom substrate. The method further includes forming a first metal layer on the top substrate and/or on the exposed first portion of the bottom substrate, forming an adhesive layer on the first metal layer, and forming a second metal layer on the adhesive layer defining one or more pads.

Method of etching microelectronic mechanical system features in a silicon wafer

A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.

Method of manufacturing a switch

MEMS switches and methods of manufacturing MEMS switches is provided. The MEMS switch having at least two cantilevered electrodes having ends which overlap and which are structured and operable to contact one another upon an application of a voltage by at least one fixed electrode.

Actuator layer patterning with topography

Provided herein is a method including fusion bonding a handle wafer to a first side of a device wafer. A hardmask is deposited on a second side of the device wafer, wherein the second side is planar. The hardmask is etched to form a MEMS device pattern and a standoff pattern. Standoffs are formed on the device wafer, wherein the standoffs are defined by the standoff pattern. A eutectic bond metal is deposited on the standoffs, the device wafer, and the hardmask. A first photoresist is deposited and removed, such that the first photoresist covers the standoffs. The eutectic bond metal is etched using the first photoresist. The MEMS device pattern is etched into the device wafer. The first photoresist and the hardmask are removed.

Low contact resistance semiconductor structure and method for manufacturing the same

A semiconductor device includes a bottom substrate, a sacrificial layer on the bottom substrate and including a first opening exposing a first portion of the bottom substrate and a second opening exposing a second portion of the bottom substrate, a top substrate on the sacrificial layer and on the second opening forming a cavity, a first metal layer on the top substrate and/or on the exposed first portion of the bottom substrate, an adhesive layer on the first metal layer, and a second metal layer on the adhesive layer defining one or more pads. The pad includes a stack-layered structure of a first metal layer on the bottom substrate, an adhesive layer on the first metal layer, and a second metal layer on the adhesive layer. The thus formed structure reduces the pad contact resistance.