A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50 C. to 450 C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.

Disclosed herein are microelectronics package architectures having self-aligned air gaps and methods of manufacturing the same. The microelectronics packages may include first and second substrates, first and second traces, and a photosensitive material. The first trace may be attached to the first substrate and comprise a first sidewall. The second trace may be attached to the first substrate and comprise a second sidewall. The second traced may be spaced a distance from the first trace with the second sidewall facing the first sidewall. First and second portions of the photosensitive material may be attached to the first and second sidewalls, respectively. The second substrate may be attached to the first and second traces. The first and second substrates and the first and second traces may form the air gap in between the first and second traces.

A process for manufacturing a microelectromechanical device envisages: providing a wafer of semiconductor material; forming a buried cavity, completely contained within the wafer, and a structural layer formed by a surface portion of the wafer and suspended over the buried cavity; forming first trenches through the structural layer as far as the buried cavity, which define the suspended structure in the structural layer; filling the first trenches and the buried cavity with sacrificial material; forming a closing structure above the structural layer; removing the sacrificial material from the first trenches and from the buried cavity to release the suspended structure, the suspended structure being isolated and buried within the wafer in a buried environment formed by the first trenches and by the buried cavity.

In accordance with an embodiment, a MEMS structure is produced on a front side of a substrate. A decoupling structure which has recesses is produced in the substrate, which decoupling structure decouples a first region from a second region of the substrate in terms of stresses. In a rear side, situated opposite the front side, of the substrate, a first cavity is produced by means of a first etching process and a second cavity is produced by means of a second etching process. The first cavity and the second cavity are produced such that the second cavity encompasses the first cavity and such that the second cavity adjoins a base region of the MEMS structure and a base region of the decoupling structure.

A method of manufacturing a semiconductor device includes providing a semiconductor structure having a bottom substrate, a sacrificial layer on the bottom substrate, and a top substrate on the sacrificial layer. The sacrificial layer has a first opening exposing a first portion of the bottom substrate and a second opening exposing a second portion of the bottom substrate. The method further includes forming a first metal layer on the top substrate and/or on the exposed first portion of the bottom substrate, forming an adhesive layer on the first metal layer, and forming a second metal layer on the adhesive layer defining one or more pads.

Disclosed herein is a micro-electro mechanical (MEMS) device including a substrate, and a MEMS mirror stack on the substrate. A first bonding layer seals against ingress of environmental contaminants and mechanically anchors the MEMS mirror stack to the substrate. A cap layer is formed on the MEMS mirror stack. A second boding layer seals against ingress of environmental contaminants and mechanically anchors the cap layer to the MEMS mirror stack.

A micro-device structure comprises a source substrate having a sacrificial layer comprising a sacrificial portion adjacent to an anchor portion, a micro-device disposed completely over the sacrificial portion, the micro-device having a top side opposite the sacrificial portion and a bottom side adjacent to the sacrificial portion and comprising an etch hole that extends through the micro-device from the top side to the bottom side, and a tether that physically connects the micro-device to the anchor portion. A micro-device structure comprises a micro-device disposed on a target substrate. Micro-devices can be any one or more of an antenna, a micro-heater, a power device, a MEMs device, and a micro-fluidic reservoir.

A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.

Methods of manufacturing a pressure sensor from an SOI wafer are provided. In preferred embodiments, the methods comprise forming a cavity in a SOI wafer by removing a first portion of a bottom silicon layer on the bottom side of the SOI wafer to a depth of an insulator layer; depositing a layer of a second material over the cavity; removing both the silicon layer and the insulator layer from a top side of the SOI wafer in a first plurality of areas above the cavity to form a diaphragm from the layer of a second material, wherein at least one support structure that spans the diaphragm is formed from material above the cavity that was not removed; and forming at least one piezoresistor in the SOI wafer over an intersection of the support structure and SOI wafer at an outside edge of the diaphragm.

A method of etching features in a silicon wafer includes coating a top surface and a bottom surface of the silicon wafer with a mask layer having a lower etch rate than an etch rate of the silicon wafer, removing one or more portions of the mask layer to form a mask pattern in the mask layer on the top surface and the bottom surface of the silicon wafer, etching one or more top surface features into the top surface of the silicon wafer through the mask pattern to a depth plane located between the top surface and the bottom surface of the silicon wafer at a depth from the top surface, coating the top surface and the one or more top surface features with a metallic coating, and etching one or more bottom surface features into the bottom surface of the silicon wafer through the mask pattern to the target depth plane.