A semiconductor device structure is provided. The semiconductor device structure includes a first substrate including a first face and a second face opposite the first face. A second substrate is bonded to the first face of the first substrate such that the second face of the first substrate faces away from the second substrate. One or more recesses are arranged in the second face of the first substrate and are configured to compensate for thermal expansion or thermal contraction.

An MEMS device includes a package, a bottom plate, and a first inertial component. The first inertial component is located in packaging space formed by the bottom plate and the package. There is a first alignment part on a surface that is of the bottom plate and that faces the packaging space, and the first inertial component has a first mounting part. A shape of the first mounting part matches a shape of the first alignment part. The MEMS device is equipped with a mounting alignment reference, the first mounting part is connected to the first alignment part, and the first inertial component is mounted on the bottom plate at a preset angle. In addition, a bottom part of the first inertial component is not directly connected to the bottom plate.

A semiconductor device that includes: a base member; a detecting element on the base member and having a first surface with a detector; an insulating protective film covering the detector and the first surface; and a resin package on the base member and including an exposure hole exposing the detector to an outside, a portion of the resin package covering the detecting element such that at least a portion of an outer periphery of the first surface is exposed through the exposure hole, and the resin package includes a recess extending along the portion of the outer periphery exposed through the exposure hole. The detecting element has: a second surface extending from the outer periphery toward the base member, a third surface extending outward from the second surface, and a fourth surface extending from the third surface toward the base member, and wherein the protective film covers the second surface.

A method includes forming a dielectric layer on a carrier wafer with a top surface and a bottom surface, wherein the top surface is positioned opposite to the bottom surface. The method includes forming a cleave layer on the dielectric layer that covers the top surface of the carrier wafer. Method includes forming a silicon Oxide layer (SiO.sub.2) over the cleave layer and coupling the Si layer to a handle wafer, wherein the handle wafer comprises silicon and wherein the handle wafer includes at least one cavity, wherein the Si layer encloses the at least one cavity. The method includes separating the carrier wafer from the handle wafer, wherein the separating forms a first wafer and a second wafer, wherein the first wafer comprises the handle wafer and the Si layer and a portion of the cleave layer, and wherein the second wafer is a reusable carrier wafer.