A semiconductor element includes a processed substrate arrangement including a processed semiconductor substrate and a metallization layer arrangement on a main surface of the processed semiconductor substrate. The semiconductor element further includes a passivation layer arranged at an outer border of the processed substrate arrangement.

A method for manufacturing an electronic device includes a stretchable member attachment step of attaching stretchable member 21 to first substrate 2 on which second substrate 3 is stacked, a first modification line formation step of forming one or more first modification lines 22 by irradiating the first substrate 2 with a laser beam, and a dividing step of stretching the stretchable member 21 to divide the first substrate 2 along the one or more first modification lines 22.

A hole plate and a MEMS microphone arrangement are disclosed. In an embodiment a hole plate includes a substrate with a first main surface, a second main surface, and a lateral surface and a perforation structure formed within the substrate, the perforation structure having a plurality of through-holes through the substrate, wherein the through-holes and the lateral surface are a result of a simultaneous dry etching step.

An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.

A semiconductor element and method are provided such that the method includes providing a processed substrate arrangement including a processed semiconductor substrate and a metallization layer structure on a main surface of the processed semiconductor substrate. The method further includes release etching for generating a kerf in the metallization layer structure at a separation region in the processed semiconductor substrate, the separation region defining a border between a die region of the processed substrate arrangement and at least a second region of the processed substrate arrangement.

A method of strain gauge fabrication is presented herein. The method includes: providing a first substrate having a cavity side; providing a second substrate having a semiconductor side; positioning the second substrate in relation to the first substrate such that the semiconductor side and the cavity side are contactable; processing the second substrate such that the first and second substrates are substantially joined via the semiconductor side and the cavity side; and etching the second substrate to define a strain gauge cantilevered over the cavity side of the first substrate.

A silicon-on-sapphire chip with minimal thermal strain preload is provided. The chip includes a sapphire substrate having a first-sapphire surface and an opposing second-sapphire surface; and a silicon layer overlaying the first-sapphire surface. The silicon layer is formed by: creating a plurality of buried cavities in a plane within tens of microns from a first-silicon surface of a silicon wafer; laser fusing the first-silicon surface to the first-sapphire surface at room temperature to attach the silicon wafer to a sapphire wafer; and cleaving the silicon wafer along the plane including the plurality of buried cavities. A silicon-wafer layer is formed from the silicon material between the first-silicon surface and the plane of the plurality of buried cavities. The silicon-wafer layer and the sapphire wafer form a silicon-on-sapphire wafer. The silicon-on-sapphire chip is formed by dicing the silicon-on-sapphire wafer.

A method of leak detection of hermetically sealed cavities semiconductor devices is provided. Scribe streets are formed with access from each packaged device on a first substrate to the edge of the first substrate. The first substrate is attached to a second substrate, forming gaps between the two substrates. A cavity is formed around a packaged device on the first substrate by attaching a bond ring to the first substrate and an optically transparent window above the bonding ring. The cavity is evacuated. A high powered laser beam strikes the top surface of the device on the first substrate within the cavity and creates a vertical surface displacement of the first substrate. The vertical surface displacement is monitored using a separate interrogation laser beam. Leakage of the cavity can be measured by characterizing the resonance decay rate, Q.

A method of leak detection of hermetically sealed cavities semiconductor devices is provided. Scribe streets are formed with access from each packaged device on a first substrate to the edge of the first substrate. The first substrate is attached to a second substrate, forming gaps between the two substrates. A cavity is formed around a packaged device on the first substrate by attaching a bond ring to the first substrate and an optically transparent window above the bonding ring. The cavity is evacuated. A high powered laser beam strikes the top surface of the device on the first substrate within the cavity and creates a vertical surface displacement of the first substrate. The vertical surface displacement is monitored using a separate interrogation laser beam. Leakage of the cavity can be measured by characterizing the resonance decay rate, Q.

The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices. Since the proposed method does not involve loading a multitude of diced chips into sockets one by one, but that a limited number of wafer strips are loaded onto corresponding strip carriers, flow jam is avoided.