A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

A method of manufacturing a semiconductor device is provided. The method includes the following operations. (a) A substrate is patterned. (b) A polymer layer is formed on the patterned substrate. (c) The polymer layer is patterned. Steps (a), (b) and (c) are repeated alternatingly. An intensity of an emission light generated by a reaction of a plasma and a product produced in steps (a), (b) and (c) is detected. An endpoint in patterning the substrate is determined according to the intensity of the emission light generated by the reaction of the plasma and the product produced in only one step of steps (a), (b) and (c). A sampling rate of the intensity is ranged from 1 pt/20 ms to 1 pt/100 ms. A smooth function is used to process the intensity of the emission light generated by the reaction of the plasma and the product.

A method can be used for producing a microelectromechanical transducer. A plurality of microelectromechanical transducers are produced on a single wafer. Each transducer includes a diaphragm. The wafer is divided into at least a first and a second region. The mechanical tensions of a random sample of diaphragms of the first region are established and the values are compared with a predetermined desired value. The mechanical tensions of a random sample of diaphragms of the second region are established and the values are compared with the predetermined desired value. The tensions of the diaphragms in the first region are adjusted to the predetermined desired value, and the tensions of the diaphragms in the second region are adjusted to the predetermined desired value.

The present disclosure discloses a method for wafer-level chip scale packaged wafer testing. The method comprises: dicing a wafer-level chip scale packaged wafer into a plurality of wafer strips each comprising a plurality of un-diced chip scale packaged devices; fixing the wafer strips onto a plurality of corresponding strip carriers respectively; testing the chip scale packaged devices of the wafer strips fixed onto the strip carriers by a testing equipment; and dicing the tested wafer strips into a plurality of individual chip scale packaged devices. Since the proposed method does not involve loading a multitude of diced chips into sockets one by one, but that a limited number of wafer strips are loaded onto corresponding strip carriers, flow jam is avoided.

A method of testing a capacitive transducer circuit, for example a MEMS capacitive transducer, by applying a test signal via one or more capacitors provided in the transducer circuit.

Systems and methods for controlling wafer-breaker devices. In some embodiments, a controller for a semiconductor wafer singulation apparatus can be configured to receive an input signal having information about at least one singulation parameter. The controller can be further configured to generate an output signal based on the input signal to effectuate an operation associated with the singulation parameter. The controller can be further configured to disable manual control of the singulation parameter. In some embodiments, such a controller can be implemented, for example, in a control module, in a kit for modifying an existing singulation apparatus, as an integral part of a singulation apparatus, or any combination thereof.

Microelectromechanical device with a carrier substrate having a substrate surface (100a), and plural MEMS modules (120. Each module includes an ASIC layer (140) having a front side (140a) and a rear side (140b). A baseplate (160) has a front side (160a) and a rear side (160b), a plurality of microelectromechanical components (130) have rear sides (130b). The baseplate rear side is cohesively connected to the ASIC layer front side with electrical contacts (144). The components are arranged on the baseplate front side with their component rear sides. The contacts are partly encompassed by a frame (195) arranged between baseplate and ASIC layer. The ASIC layer has an ASIC controlling the components. The ASIC is electrically connected to the components using a portion of the contacts. The modules are arranged on the substrate surface and the ASIC layer rear sides of the modules are connected to the substrate surface.

A system for reducing electromotive force (EMF) errors is disclosed. The system may include a circuit component with a plurality of leads soldered to a circuit board. The system may also include a filler material coupled to at least a first lead of the plurality of leads. The system may exhibit an asymmetrical thermal conduction of the first lead relative to a different lead of the plurality of leads due to the filler material.

A machine vision system and method use lensless near-contact imaging with coherent illumination, or incoherent illumination, and high pixel count large format sensors (e.g., equivalent to at least 20 to 65 mega-pixels) to produce diffraction patterns of the micro-objects or the gray scale images of the micro-objects over a large overall field-of-view of the machine vision system. The machine vision system provides feedback to a microassembler system to position, orient, and assemble microscale devices like micro-LEDs over large working areas. The effective resolution of the machine vision system can be further improved through the use of gray scale and super-resolution image processing techniques.

According to an implementation, a method for manufacturing a microelectromechanical system mirror device is provided. A mirror portion of the mirror device is rotatable about a first axis having an associated first resonance frequency and a second axis different from the first axis and having an associated second resonance frequency. The method includes estimating a deviation of a first geometry parameter of the mirror device from a reference value, and adjusting a manufacturing step for the mirror device to modify a second geometry parameter of the mirror device different from the first geometry parameter such that a variation of a frequency ratio between the first resonance frequency and the second resonance frequency caused by the deviation of the first geometry parameter and the modifying of the second geometry parameter is below a predefined threshold.