B81C2203/0118

Stacked-die MEMS resonator

A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

Undercut-free patterned aluminum nitride structure and methods for forming the same

A microstructure may be provided by forming a metal layer such as a molybdenum layer over a substrate. An aluminum nitride layer is formed on a top surface of the metal layer. A surface portion of the aluminum nitride layer is converted into a continuous aluminum oxide-containing layer by oxidation. A dielectric spacer layer may be formed over the continuous aluminum oxide-containing layer. Contact via cavities extending through the dielectric spacer layer, the continuous aluminum oxide-containing layer, and the aluminum nitride layer and down to a respective portion of the at least one metal layer may be formed using etch processes that contain a wet etch step while suppressing formation of an undercut in the aluminum nitride layer. Contact via structures may be formed in the contact via cavities. The microstructure may include a micro-electromechanical system (MEMS) device containing a piezoelectric transducer.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

A semiconductor device includes: a substrate; a transduction microstructure integrated in the substrate; a cap joined to the substrate and having a first face adjacent to the substrate and a second, outer, face; and a channel extending through the cap from the second face to the first face and communicating with the transduction microstructure. A protective membrane made of porous polycrystalline silicon permeable to aeriform substances is set across the channel.

Device for protecting FEOL element and BEOL element

A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.

Apparatus and methods for wafer to wafer bonding
11335607 · 2022-05-17 · ·

A method includes having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based on the physical parameter of the first wafer; obtaining measurements of the first wafer to obtain the physical parameter of the first wafer; generating, by the model, the first wafer bonding recipe based on the physical parameter of the first wafer; and bonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer.

HERMETICALLY SEALED TRANSPARENT CAVITY AND PACKAGE FOR SAME

A hermetically sealed package includes: at least one cover substrate and a substrate arranged so as to adjoin the at least one cover substrate, which together define at least part of the package, the at least one cover substrate being in a thermally prestressed state and bonded to the substrate adjoining the at least one cover substrate in a hermetically sealing manner by at least one laser bonding line, the at least one cover substrate being made of a material which has a different characteristic value of a coefficient of thermal expansion than the adjoining substrate and a thermal prestress is established in the package; and at least one functional area enclosed in the package.

HERMETICALLY SEALED, TOUGHENED GLASS PACKAGE AND METHOD FOR PRODUCING SAME

A hermetically sealed package includes: a base substrate and a cover substrate which define at least part of the package, the base substrate and the cover substrate being hermetically sealed to one another by at least one laser bonding line, the at least one laser bonding line having a height perpendicular to its bonding plane, at least the cover substrate including a toughened layer at its surface, at least on a side opposite the at least one laser bonding line; and at least one functional area enclosed in the package.

MEMS device and manufacturing method thereof

A manufacturing method of microelectromechanical system (MEMS) device includes providing a first, a second and a third substrates, wherein the first substrate includes a first and a second circuit, the second substrate includes second and third connection areas, and the third substrate includes first connection areas. Second grooves and a dividing groove are formed on the fourth surface of the third substrate. The second and third substrates are bonded to make the first and the second connection areas correspondingly connect with each other. The second substrate is divided to form electrically isolating first and second movable elements. The first movable element is spatial separated from the third substrate and corresponding to the second groove. The second movable element is connected to the third substrate. The first and the second substrates are bonded to make the fourth and the third connection areas connect correspondingly. The third substrate is thinned, divided into a first and a second cap from the dividing groove, and formed a first groove from the fifth surface. The first cap is corresponding to the first movable element and the first circuit. Air tight space to sense a pressure variation of exterior environment is formed between the first substrate and the second cap. The second movable element is movable with the second cap by the pressure variation of the exterior environment. Accordingly, the pressure sensor and the MEMS structure for sensing other physical quantity can be integrated in the foregoing MEMS device by a single process.

Method to form a rough crystalline surface

Various embodiments of the present disclosure are directed towards a method to roughen a crystalline layer. A crystalline layer is deposited over a substrate. A mask material is diffused into the crystalline layer along grain boundaries of the crystalline layer. The crystalline layer and the mask material may, for example, respectively be or comprise polysilicon and silicon oxide. Other suitable materials are, however, amenable. An etch is performed into the crystalline layer with an etchant having a high selectivity for the crystalline layer relative to the mask material. The mask material defines micro masks embedded in the crystalline layer along the grain boundaries. The micro masks protect underlying portions of the crystalline layer during the etch, such that the etch forms trenches in the crystalline layer where unmasked by the micro masks.

Method of room temperature covalent bonding

A method of bonding includes using a bonding layer having a fluorinated oxide. Fluorine may be introduced into the bonding layer by exposure to a fluorine-containing solution, vapor or gas or by implantation. The bonding layer may also be formed using a method where fluorine is introduced into the layer during its formation. The surface of the bonding layer is terminated with a desired species, preferably an NH.sub.2 species. This may be accomplished by exposing the bonding layer to an NH.sub.4OH solution. High bonding strength is obtained at room temperature. The method may also include bonding two bonding layers together and creating a fluorine distribution having a peak in the vicinity of the interface between the bonding layers. One of the bonding layers may include two oxide layers formed on each other. The fluorine concentration may also have a second peak at the interface between the two oxide layers.