A manufacturing method of a carrier for a double-side polishing apparatus, including: preparing a carrier base material and insert thicker than the carrier base material, inserting the insert into a holding hole so as to protrude the insert from both sides of the front surface and back surface of the carrier base material, measuring each of a front protruding amount of the insert protruded from front surface of the carrier base material and a back protruding amount of the insert protruded from back surface of the carrier base material, setting each rotational speed of the upper turn table and lower turn table in starting-up polishing of the carrier so as to decrease the difference between the front protruding amount and back protruding amount, and a starting-up polishing step to subject the carrier to starting-up polishing at each set rotational speed of the upper turn table and the lower turn table.

A manufacturing method of a carrier for a double-side polishing apparatus, including: preparing a carrier base material and insert thicker than the carrier base material, inserting the insert into a holding hole so as to protrude the insert from both sides of the front surface and back surface of the carrier base material, measuring each of a front protruding amount of the insert protruded from front surface of the carrier base material and a back protruding amount of the insert protruded from back surface of the carrier base material, setting each rotational speed of the upper turn table and lower turn table in starting-up polishing of the carrier so as to decrease the difference between the front protruding amount and back protruding amount, and a starting-up polishing step to subject the carrier to starting-up polishing at each set rotational speed of the upper turn table and the lower turn table.

A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80 Shore A, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished. The upper and lower surfaces form a polishing gap extending from the inner edge to the outer edge. A height of the polishing gap at the inner edge differs linearly from the height of the polishing gap at the outer edge.

A method for polishing at least one wafer composed of semiconductor material that has a front side and the rear side includes performing at least one first polishing step including simultaneously polishing both front and rear sides of the at least one wafer at a process temperature between an upper polishing plate and a lower polishing plate. Each of the upper polishing and lower polishing plates is covered with a polishing pad having an inner edge and an outer edge, a hardness of at least 80 Shore A, a compressibility of less than 2.5%, and respective upper and lower surfaces that come into contact with the wafer being polished. The upper and lower surfaces form a polishing gap extending from the inner edge to the outer edge. A height of the polishing gap at the inner edge differs linearly from the height of the polishing gap at the outer edge.

Provided are a method for polishing a silicon substrate according to which PID can be reduced and a polishing composition set usable in the polishing method. The silicon substrate polishing method provided by this invention comprises a stock polishing step and a final polishing step. The stock polishing step comprises several stock polishing sub-steps carried out on one same platen. The several stock polishing sub-steps comprise a final stock polishing sub-step carried out while supplying a final stock polishing slurry P.sub.F to the silicon substrate. The total amount of the final stock polishing slurry P.sub.F supplied to the silicon substrate during the final stock polishing sub-step has a total weight of Cu and a total weight of Ni, at least one of which being 1 ?g or less.

Provided are a method for polishing a silicon substrate according to which PID can be reduced and a polishing composition set usable in the polishing method. The silicon substrate polishing method provided by this invention comprises a stock polishing step and a final polishing step. The stock polishing step comprises several stock polishing sub-steps carried out on one same platen. The several stock polishing sub-steps comprise a final stock polishing sub-step carried out while supplying a final stock polishing slurry P.sub.F to the silicon substrate. The total amount of the final stock polishing slurry P.sub.F supplied to the silicon substrate during the final stock polishing sub-step has a total weight of Cu and a total weight of Ni, at least one of which being 1 ?g or less.

One aspect of embodiment provides a wafer polishing chamber, including a wafer transfer part; a polishing part provided with an upper surface plate and lower surface plate, and configured to polish the wafer transferred from the wafer transfer part; a partition wall configured to separate positions where the transfer part and the polishing part are disposed; a plurality of fan units configured to introduce air; and a plurality of exhaust units configured to exhaust air, wherein the fan unit may be provided in at least one in an upper portion of the polishing part.

Apparatuses and methods for performing a post-CMP cleaning are provided. The apparatus includes a chamber configured to receive a wafer in need of having CMP residue removed. The apparatus also includes a spray unit configured to apply a first cleaning solution to at least one surface of the wafer. The apparatus further includes a brush cleaner configured to scrub the at least one surface of the wafer. In addition, the apparatus includes at least one inner tank disposed in the chamber for storing a second cleaning solution that is used to clean the brush cleaner.

Apparatuses and methods for performing a post-CMP cleaning are provided. The apparatus includes a chamber configured to receive a wafer in need of having CMP residue removed. The apparatus also includes a spray unit configured to apply a first cleaning solution to at least one surface of the wafer. The apparatus further includes a brush cleaner configured to scrub the at least one surface of the wafer. In addition, the apparatus includes at least one inner tank disposed in the chamber for storing a second cleaning solution that is used to clean the brush cleaner.

A machining apparatus for a workpieces includes an upper turn table support mechanism supporting an upper turn table from above to be vertically movable by a cylinder extending along a rotational axis direction of the table, a horizontal plate fixed to the cylinder so that a main surface thereof becomes perpendicular to a longitudinal axis of the cylinder, at least three displacement sensors which measure horizontal plate surface height positions when the upper turn table has moved down to a fixed position, and a control apparatus to calculate a relative upper turn table height position and an angle formed between the upper turn table rotational axis and the cylinder longitudinal axis from the horizontal plate surface height positions measured by the displacement sensors. A workpiece holding abnormality can be accurately and quickly detected before machining the workpiece to avoid damage, and an cylinder eccentric angle can be detected during machining.