Patent classifications
B81B2201/018
ELECTROMECHANICAL RELAY DEVICE
A electromechanical relay device (100) comprising a source electrode (102), a beam (104) mounted on the source electrode at a first end and electrically coupled to the source electrode; a first drain electrode (112) located adjacent a second end of the beam, wherein a first contact (110) on the beam is arranged to be separated from a second contact (112) on the first drain electrode when the relay device is in a first condition; a first gate electrode (106 arranged to cause the beam to deflect, to electrically couple the first contact and the second contact such that the device is in a second condition; and wherein the first and second contacts are each coated with a layer of nanocrystalline graphite.
Merged legs and semi-flexible anchoring having cantilevers for MEMS device
The present invention generally relates to a MEMS device having a plurality of cantilevers that are coupled together in an anchor region and/or by legs that are coupled in a center area of the cantilever. The legs ensure that each cantilever can move/release from above the RF electrode at the same voltage. The anchor region coupling matches the mechanical stiffness in all sections of the cantilever so that all of the cantilevers move together.
Computation devices and artificial neurons based on nanoelectromechanical systems
Techniques, systems, and devices are described for implementing for implementing computation devices and artificial neurons based on nanoelectromechanical (NEMS) systems. In one aspect, a nanoelectromechanical system (NEMS) based computing element includes: a substrate; two electrodes configured as a first beam structure and a second beam structure positioned in close proximity with each other without contact, wherein the first beam structure is fixed to the substrate and the second beam structure is attached to the substrate while being free to bend under electrostatic force. The first beam structure is kept at a constant voltage while the other voltage varies based on an input signal applied to the NEMS based computing element.
Zero Power Plasmonic Microelectromechanical Device
A zero-power plasmonic microelectromechanical system (MEMS) device is capable of specifically sensing electromagnetic radiation and performing signal processing operations. Such devices are highly sensitive relays that consume no more than 10 nW of power, utilizing the energy in detected electromagnetic radiation to detect and discriminate a target without the need of any additional power source. The devices can continuously monitor an environment and wake up an electronic circuit upon detection of a specific trigger signature of electromagnetic radiation, such as vehicular exhaust, gunfire, an explosion, a fire, a human or animal, and a variety of sources of radiation from the ultraviolet to visible light, to infrared, to terahertz radiation.
MEMS SWITCH DEVICE AND ELECTRONIC APPARATUS
The present disclosure provides an MEMS switch device and an electronic apparatus. The MEMS switch device includes a base substrate, a membrane bridge structure, and a first ground line, a signal line and a second ground line sequentially arranged on a first side surface of the base substrate at intervals; the membrane bridge structure has a first end electrically connected to the first ground line, and a second end, opposite to the first end, electrically connected to the second ground line; and the membrane bridge structure includes a membrane bridge body structure and at least one protruding structure on the membrane bridge body structure, where the protruding structure protrudes from the membrane bridge body structure in a direction perpendicular to the first side surface of the base substrate.
Thermal metamaterial for low power MEMS thermal control
A thermal metamaterial device comprises at least one MEMS thermal switch, including a substrate layer including a first material having a first thermal conductivity, and a thermal bus over a first portion of the substrate layer. The thermal bus includes a second material having a second thermal conductivity higher than the first thermal conductivity. An insulator layer is over a second portion of the substrate layer and includes a third material that is different from the first and second materials. A thermal pad is supported by a first portion of the insulator layer, the thermal pad including the second material and having an overhang portion located over a portion of the thermal bus. When a voltage is applied to the thermal pad, an electrostatic interaction occurs to cause a deflection of the overhang portion toward the thermal bus, thereby providing thermal conductivity between the thermal pad and the thermal bus.
SEMICONDUCTOR STRUCTURES PROVIDED WITHIN A CAVITY AND RELATED DESIGN STRUCTURES
Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension.
Multiaxial strain engineering of defect doped materials
Compositions and methods related to multiaxially straining defect doped materials as well as their use in electrical circuits are generally described.
Semiconductor structures provided within a cavity and related design structures
Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity. The method for forming the cavity further includes forming at least one first vent hole of a first dimension which is sized to avoid or minimize material deposition on a beam structure during sealing processes. The method for forming the cavity further includes forming at least one second vent hole of a second dimension, larger than the first dimension.
VANISHING VIA FOR HARDWARE IP PROTECTION FROM REVERSE ENGINEERING
A semiconductor device can include a first metal trace, a first via disposed on the first metal trace, a second metal trace disposed on the first via, and an insulator interposed between the first metal trace and the first via. The insulator can be configured to lower an energy barrier or redistribute structure defects or charge carriers, such that the first metal trace and the first via are electrically connected to each other when power is applied. The semiconductor device can further include a dummy via disposed on the first metal trace.